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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
DS152 (v2.10) October18, 2010 Advance Product Specification
Virtex-6 FPGA Electrical Characteristics
Virtex(R)-6 FPGAs are available in -3, -2, -1, and -1L speed grades, with -3 having the highest performance. Virtex-6 FPGA DC and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices might be available in the industrial range. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. This Virtex-6 FPGA data sheet, part of an overall set of documentation on the Virtex-6 family of FPGAs, is available on the Xilinx website. All specifications are subject to change without notice.
Virtex-6 FPGA DC Characteristics
Table 1: Absolute Maximum Ratings (1)
Symbol
VCCINT VCCAUX VCCO VBATT VFS VREF VIN(3) VTS TSTG TSOL Tj Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. When not programming eFUSE, connect VFS to GND. 2.5V I/O absolute maximum limit applied to DC and AC signals. For I/O operation, refer to the Virtex-6 FPGA SelectIO Resources User Guide. For soldering guidelines and thermal considerations, see Virtex-6 FPGA Packaging and Pinout Specification.
Description
Internal supply voltage relative to GND For -1L devices: Internal supply voltage relative to GND Auxiliary supply voltage relative to GND Output drivers supply voltage relative to GND Key memory battery backup supply External voltage supply for eFUSE programming(2) Input reference voltage 2.5V or below I/O input voltage relative to GND(4) (user and dedicated I/Os) Voltage applied to 3-state 2.5V or below output(4) (user and dedicated I/Os) Storage temperature (ambient) Maximum soldering temperature(5) Maximum junction temperature(5) -0.5 to 1.1 -0.5 to 1.0 -0.5 to 3.0 -0.5 to 3.0 -0.5 to 3.0 -0.5 to 3.0 -0.5 to 3.0 -0.5 to VCCO + 0.5 -0.5 to VCCO + 0.5 -65 to 150 +220 +125
Units
V V V V V V V V V C C C
2. 3. 4. 5.
(c) 2009-2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 2: Recommended Operating Conditions
Symbol Description
Internal supply voltage relative to GND, Tj = 0C to +85C VCCINT For -1L commercial temperature range devices: internal supply voltage relative to GND, Tj = 0C to +85C For -1L industrial temperature range devices: internal supply voltage relative to GND, Tj = -40C to +100C VCCAUX VCCO(1)(3)(4) VIN IIN(6) VBATT(2) VFS(7) Notes:
1. 2. 3. 4. 5. 6. 7. Configuration data is retained even if VCCO drops to 0V. VBATT is required only when using bitstream encryption. If battery is not used, connect VBATT to either ground or VCCAUX. Includes VCCO of 1.2V, 1.5V, 1.8V, and 2.5V. The configuration supply voltage VCC_CONFIG is also known as VCCO_0. All voltages are relative to ground. A total of 100 mA per bank should not be exceeded. When not programming eFUSE, connect VFS to GND.
Min
0.95 0.87 0.91 2.375 1.14 GND - 0.20 GND - 0.20 - 1.0 2.375
Max
1.05 0.93 0.97 2.625 2.625 2.625 VCCO + 0.2 10 2.5 2.625
Units
V V V V V V V mA V V
Auxiliary supply voltage relative to GND, Tj = 0C to +85C Supply voltage relative to GND, Tj = 0C to +85C 2.5V supply voltage relative to GND, Tj = 0C to +85C 2.5V and below supply voltage relative to GND, Tj = 0C to +85C Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. Battery voltage relative to GND, Tj = 0C to +85C External voltage supply for eFUSE programming
Table 3: DC Characteristics Over Recommended Operating Conditions (1)(2)
Symbol
VDRINT VDRI IREF IL CIN(3)
Description
Data retention VCCINT voltage (below which configuration data might be lost) Data retention VCCAUX voltage (below which configuration data might be lost) VREF leakage current per pin Input or output leakage current per pin (sample-tested) Die input capacitance at the pad Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V
Min
0.75 2.0 - - - 20 8 5 1 3 - - -
Typ
- - - - - - - - - - - 1.0002 5
Max
- - 10 10 8 80 40 30 20 80 150 - -
Units
V V A A pF A A A A A nA n
IRPU
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V Pad pull-down (when selected) @ VIN = 2.5V Battery supply current Temperature diode ideality factor Series resistance
IRPD IBATT n r Notes:
1. 2. 3.
Typical values are specified at nominal voltage, 25C. Maximum value specified for worst case process at 25C. This measurement represents the die capacitance at the pad, not including the package.
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Important Note
Typical values for quiescent supply current are specified at nominal voltage, 85C junction temperatures (Tj). Xilinx recommends analyzing static power consumption at Tj = 85C because the majority of designs operate near the high end of the commercial temperature range. Quiescent supply current is specified by speed grade for Virtex-6 devices. Use the XPOWERTM Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate static power consumption for conditions other than those specified in Table 4. Table 4: Typical Quiescent Supply Current
Symbol
ICCINTQ
Description
Quiescent VCCINT supply current
Device
XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T
Speed and Temperature Grade -3 (C)
927 1563 2059 2478 3001 N/A N/A 3476 N/A 2906
-2 (C & I)(1)
927 1563 2059 2478 3001 4515 5094 3476 5227 2906
-1 (C & I)
927 1563 2059 2478 3001 4515 5094 3476 5227 2906
-1L (C)
656 1102 1441 1733 2092 3147 3471 2409 3622 N/A N/A N/A
-1L (I)(2)
741 1245 1628 1957 2363 3555 3921 2721 4091 N/A N/A N/A N/A 1 1 1 2 2 3 3 2 2 N/A N/A N/A N/A
Units
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
N/A 1 1 1 2 2 N/A N/A 2 N/A 1 1 1 1 2 2 3 3 2 2 1 1 1 1 2 2 3 3 2 2 1
N/A 1 1 1 2 2 3 3 2 2 N/A N/A N/A
ICCOQ
Quiescent VCCO supply current
XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T
N/A
N/A
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics Table 4: Typical Quiescent Supply Current (Cont'd)
Symbol
ICCAUXQ
Description
Quiescent VCCAUX supply current
Device
XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T
Speed and Temperature Grade -3 (C)
45 75 113 135 191 N/A N/A 186 N/A 152
-2 (C & I)(1)
45 75 113 135 191 286 387 186 279 152
-1 (C & I)
45 75 113 135 191 286 387 186 279 152
-1L (C)
45 75 113 135 191 286 387 186 279 N/A N/A N/A
-1L (I)(2)
45 75 113 135 191 286 387 186 279 N/A N/A N/A N/A
Units
mA mA mA mA mA mA mA mA mA mA mA mA mA
N/A
N/A
Notes:
1. 2. The XC6VLX550T, XC6VLX760, XC6VSX475T, and XC6VHX565T are not offered in -2I. Typical values are specified at nominal voltage, 85C junction temperatures (Tj). -1, -2, and -3 industrial (I) grade devices have the same typical values as commercial (C) grade devices at 85C, but higher values at 100C. Use the XPE tool to calculate 100C values. -1L industrial grade devices have the values specified in this column. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools.
3. 4.
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device initialization. The actual current consumed depends on the power-on ramp rate of the power supply. Virtex-6 devices require a power-on sequence of VCCINT, VCCAUX, and VCCO. If the requirement can not be met, then VCCAUX must always be powered prior to VCCO. VCCAUX and VCCO can be powered by the same supply, therefore, both VCCAUX and VCCO are permitted to ramp simultaneously. Similarly, for the power-down sequence, VCCO must be powered down prior to VCCAUX or if power by the same supply, VCCAUX and VCCO power-down simultaneously. Table 5 shows the minimum current, in addition to ICCQ, that are required by Virtex-6 devices for proper power-on and configuration. If the current minimums shown in Table 4 and Table 5 are met, the device powers on after all three supplies have passed through their power-on reset threshold voltages. The FPGA must be configured after VCCINT is applied. Once initialized and configured, use the XPOWER tools to estimate current drain on these supplies. Table 5: Power-On Current for Virtex-6 Devices
Device
XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T Notes:
1. 2. Typical values are specified at nominal voltage, 25C. Use the XPOWERTM Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate maximum power-on currents.
ICCINTMIN Typ(1)
See ICCINTQ in Table 4 See ICCINTQ in Table 4 See ICCINTQ in Table 4 See ICCINTQ in Table 4 See ICCINTQ in Table 4 See ICCINTQ in Table 4 See ICCINTQ in Table 4 See ICCINTQ in Table 4 See ICCINTQ in Table 4 See ICCINTQ in Table 4
ICCAUXMIN Typ(1)
ICCAUXQ + 10 ICCAUXQ + 10 ICCAUXQ + 40 ICCAUXQ + 40 ICCAUXQ + 40 ICCAUXQ + 40 ICCAUXQ + 40 ICCAUXQ + 40 ICCAUXQ + 50 ICCAUXQ + 40
ICCOMIN Typ(1)
ICCOQ + 30 mA per bank ICCOQ + 30 mA per bank ICCOQ + 30 mA per bank ICCOQ + 30 mA per bank ICCOQ + 30 mA per bank ICCOQ + 30 mA per bank ICCOQ + 30 mA per bank ICCOQ + 30 mA per bank ICCOQ + 30 mA per bank ICCOQ + 30 mA per bank
Units
mA mA mA mA mA mA mA mA mA mA mA mA mA
Table 6: Power Supply Ramp Time
Symbol
VCCINT VCCO VCCAUX
Description
Internal supply voltage relative to GND Output drivers supply voltage relative to GND Auxiliary supply voltage relative to GND
Ramp Time
0.20 to 50.0 0.20 to 50.0 0.20 to 50.0
Units
ms ms ms
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
SelectIOTM DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Table 7: SelectIO DC Input and Output Levels
I/O Standard
LVCMOS25, LVDCI25 LVCMOS18, LVDCI18 LVCMOS15, LVDCI15 LVCMOS12 HSTL I_12 HSTL I(2) HSTL II(2) HSTL III(2) DIFF HSTL I(2) DIFF HSTL II(2) SSTL2 I SSTL2 II DIFF SSTL2 I DIFF SSTL2 II SSTL18 I SSTL18 II DIFF SSTL18 I DIFF SSTL18 II SSTL15 Notes:
1. 2. 3. 4. 5. 6. Tested according to relevant specifications. Applies to both 1.5V and 1.8V HSTL. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA. Supported drive strengths of 2, 4, 6, or 8 mA. For detailed interface specific DC voltage levels, see the Virtex-6 FPGA SelectIO Resources User Guide.
VIL V, Min
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
VIH V, Max
0.7
VOL V, Max
VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3
VOH V, Min
VCCO - 0.4 VCCO - 0.45 75% VCCO 75% VCCO 75% VCCO VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 - - VTT + 0.61 VTT + 0.81 - - VTT + 0.47 VTT + 0.60 - - VTT + 0.175
IOL mA
Note(3) Note(4) Note(4) Note(5) 6.3 8 16 24 - - 8.1 16.2 - - 6.7 13.4 - - 14.3
IOH mA
Note(3) Note(4) Note(4) Note(5) 6.3 -8 -16 -8 - - -8.1 -16.2 - - -6.7 -13.4 - - 14.3
V, Min
1.7 65% VCCO 65% VCCO 65% VCCO VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1
V, Max
0.4 0.45 25% VCCO 25% VCCO 25% VCCO 0.4 0.4 0.4 - - VTT - 0.61 VTT - 0.81 - - VTT - 0.47 VTT - 0.60 - - VTT - 0.175
35% VCCO 35% VCCO 35% VCCO VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1
50% VCCO - 0.1 50% VCCO + 0.1 50% VCCO - 0.1 50% VCCO + 0.1 VREF - 0.15 VREF - 0.15 50% VCCO - 0.15 50% VCCO - 0.15 VREF - 0.125 VREF - 0.125 50% VCCO - 0.125 50% VCCO - 0.125 VREF - 0.1 VREF + 0.15 VREF + 0.15 50% VCCO + 0.15 50% VCCO + 0.15 VREF + 0.125 VREF + 0.125 50% VCCO + 0.125 50% VCCO + 0.125 VREF + 0.1
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
HT DC Specifications (HT_25)
Table 8: HT DC Specifications
Symbol
VCCO VOD VOD VOCM VOCM VID VID VICM VICM
DC Parameter
Supply Voltage Differential Output Voltage Change in VOD Magnitude Output Common Mode Voltage Change in VOCM Magnitude Input Differential Voltage Change in VID Magnitude Input Common Mode Voltage Change in VICM Magnitude
Conditions
RT = 100 across Q and Q signals RT = 100 across Q and Q signals
Min
2.38 480 -15 440 -15 200 -15 440 -15
Typ
2.5 600 - 600 - 600 - 600 -
Max
2.63 885 15 760 15 1000 15 780 15
Units
V mV mV mV mV mV mV mV mV
LVDS DC Specifications (LVDS_25)
Table 9: LVDS DC Specifications
Symbol
VCCO VOH VOL VODIFF VOCM VIDIFF VICM
DC Parameter
Supply Voltage Output High Voltage for Q and Q Output Low Voltage for Q and Q Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High Output Common-Mode Voltage Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High Input Common-Mode Voltage
Conditions
RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals
Min
2.38 - 0.825 247 1.075 100 0.3
Typ
2.5 - - 350 1.250 350 1.2
Max
2.63 1.675 - 600 1.425 600 2.2
Units
V V V mV V mV V
Extended LVDS DC Specifications (LVDSEXT_25)
Table 10: Extended LVDS DC Specifications
Symbol
VCCO VOH VOL VODIFF VOCM VIDIFF VICM
DC Parameter
Supply Voltage Output High Voltage for Q and Q Output Low Voltage for Q and Q Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High Output Common-Mode Voltage Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High Input Common-Mode Voltage
Conditions
RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals Common-mode input voltage = 1.25V Differential input voltage = 350 mV
Min
2.38 - 0.715 350 1.075 100 0.3
Typ
2.5 - - - 1.250 - 1.2
Max
2.63 1.785 - 840 1.425 1000 2.2
Units
V V V mV V mV V
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
LVPECL DC Specifications (LVPECL_25)
These values are valid when driving a 100 differential load only, i.e., a 100 resistor between the two receiver pins. The VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode ranges. Table 11 summarizes the DC output specifications of LVPECL. For more information on using LVPECL, see the Virtex-6 FPGA SelectIO Resources User Guide. Table 11: LVPECL DC Specifications
Symbol
VOH VOL VICM VIDIFF Notes:
1. 2. Recommended input maximum voltage not to exceed VCCAUX + 0.2V. Recommended input minimum voltage not to go below -0.5V.
DC Parameter
Output High Voltage Output Low Voltage Input Common-Mode Voltage Differential Input Voltage(1)(2)
Min
VCC - 1.025 VCC - 1.81 0.6 0.100
Typ
1.545 0.795 - -
Max
VCC - 0.88 VCC - 1.62 2.2 1.5
Units
V V V V
eFUSE Read Endurance
Table 12 lists the maximum number of read cycle operations expected. For more information, see the Virtex-6 FPGA Configuration User Guide. Table 12: eFUSE Read Endurance
Symbol
DNA_CYCLES AES_CYCLES
Description
Number of DNA_PORT READ operations or JTAG ISC_DNA read command operations. Unaffected by SHIFT operations. Number of JTAG FUSE_KEY or FUSE_CNTL read command operations. Unaffected by SHIFT operations.
Speed Grade -3 -2 -1 -1L
Units
Read Cycles Read Cycles
30,000,000 30,000,000
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
GTX Transceiver Specifications
GTX Transceiver DC Characteristics
Table 13: Absolute Maximum Ratings for GTX Transceivers(1)
Symbol
MGTAVCC MGTAVTT MGTAVTTRCAL VIN VMGTREFCLK Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Description
Analog supply voltage for the GTX transmitter and receiver circuits relative to GND Analog supply voltage for the GTX transmitter and receiver termination circuits relative to GND Analog supply voltage for the resistor calibration circuit of the GTX transceiver column Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage Reference clock absolute input voltage
Min
-0.5 -0.5 -0.5 -0.5 -0.5
Max
1.1 1.32 1.32 1.32 1.32
Units
V V V V V
Table 14: Recommended Operating Conditions for GTX Transceivers(1)(2)
Symbol Description Speed Grade
-3, -2(3) MGTAVCC Analog supply voltage for the GTX transmitter and receiver circuits relative to GND -3, -2(3) -1 -1L MGTAVTT MGTAVTTRCAL Notes:
1. 2. 3. Each voltage listed requires the filter circuit described in Virtex-6 FPGA GTX Transceivers User Guide. Voltages are specified for the temperature range of Tj = -40C to +100C. If a GTX Quad contains transceivers operating with a mixture of PLL frequencies above and below 2.7 GHz, the MGTAVCC voltage supply must be in the range of 1.0V to 1.06V.
PLL Frequency
> 2.7 GHz 2.7 GHz 2.7 GHz 2.7 GHz - -
Min
1.0 0.95 0.95 0.95 1.14 1.14
Typ
1.03 1.0 1.0 1.0 1.2 1.2
Max
1.06 1.06 1.06 1.05 1.26 1.26
Units
V V V V V V
Analog supply voltage for the GTX transmitter and receiver termination circuits relative to GND Analog supply voltage for the resistor calibration circuit of the GTX transceiver column
All All
Table 15: GTX Transceiver Supply Current (per Lane) (1)(2)
Symbol
IMGTAVTT IMGTAVCC MGTRREF Notes:
1. 2. Typical values are specified at nominal voltage, 25C, with a 3.125 Gb/s line rate. Values for currents of other transceiver configurations and conditions can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools.
Description
MGTAVTT supply current for one GTX transceiver MGTAVCC supply current for one GTX transceiver Precision reference resistor for internal calibration termination
Typ
55.9 56.1
Max
Note 2
Units
mA mA
100.0 1% tolerance
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 16: GTX Transceiver Quiescent Supply Current (per Lane) (1)(2)(3)
Symbol
IMGTAVTTQ IMGTAVCCQ Notes:
1. 2. 3. 4. Device powered and unconfigured. Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools. GTX transceiver quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of available GTX transceivers. Typical values are specified at nominal voltage, 25C.
Description
Quiescent MGTAVTT supply current for one GTX transceiver Quiescent MGTAVCC supply current for one GTX transceiver
Typ(4)
0.9 3.5
Max
Note 2
Units
mA mA
GTX Transceiver DC Input and Output Levels
Table 17 summarizes the DC output specifications of the GTX transceivers in Virtex-6 FPGAs. Consult the Virtex-6 FPGA GTX Transceivers User Guide for further details. Table 17: GTX Transceiver DC Specifications
Symbol
DVPPIN VIN VCMIN DVPPOUT VCMOUTDC RIN ROUT TOSKEW CEXT Notes:
1. 2. The output swing and preemphasis levels are programmable using the attributes discussed in the Virtex-6 FPGA GTX Transceivers User Guide and can result in values lower than reported in this table. Other values can be used as appropriate to conform to specific protocols and standards.
DC Parameter
Differential peak-to-peak input voltage Absolute input voltage Common mode input voltage
Conditions
External AC coupled 4.25 Gb/s External AC coupled > 4.25 Gb/s DC coupled MGTAVTT = 1.2V DC coupled MGTAVTT = 1.2V
Min
125 175 -400 - -
Typ
- - - 2/3 MGTAVTT -
Max
2000 2000 MGTAVTT - 1000
Units
mV mV mV mV mV mV
Differential peak-to-peak output Transmitter output swing is set to voltage (1) maximum setting DC common mode output voltage. Differential input resistance Differential output resistance Transmitter output pair (TXP and TXN) intra-pair skew Recommended external AC coupling capacitor(2) Equation based
MGTAVTT - DVPPOUT/4 80 80 - - 100 100 2 100 130 120 8 -
ps nF
X-Ref Target - Figure 1
+V
P
Single-Ended Voltage
ds152_01_121509
N 0
Figure 1: Single-Ended Peak-to-Peak Voltage
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
X-Ref Target - Figure 2
+V
0
Differential Voltage
-V
P-N
ds152_02_121509
Figure 2: Differential Peak-to-Peak Voltage Table 18 summarizes the DC specifications of the clock input of the GTX transceiver. Consult the Virtex-6 FPGA GTX Transceivers User Guide for further details. Table 18: GTX Transceiver Clock DC Input Level Specification
Symbol
VIDIFF RIN CEXT
DC Parameter
Differential peak-to-peak input voltage Differential input resistance Required external AC coupling capacitor
Conditions
Min
210 90 -
Typ
800 100 100
Max
2000 130 -
Units
mV nF
GTX Transceiver Switching Characteristics
Consult Virtex-6 FPGA GTX Transceivers User Guide for further information. Table 19: GTX Transceiver Performance
Symbol
FGTXMAX FGPLLMAX FGPLLMIN Notes:
1. See Table 14 for MGTAVCC requirements when PLL frequency is greater than 2.7 GHz.
Description
Maximum GTX transceiver data rate Maximum PLL frequency Minimum PLL frequency
Speed Grade -3
6.6 3.3(1) 1.2
-2
6.6 3.3(1) 1.2
-1
5.0 2.7 1.2
-1L
5.0 2.7 1.2
Units
Gb/s GHz GHz
Table 20: GTX Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol
FGTXDRPCLK
Description
GTXDRPCLK maximum frequency
Speed Grade -3
150
-2
150
-1
125
-1L
100
Units
MHz
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 21: GTX Transceiver Reference Clock Switching Characteristics
Symbol
FGCLK TRCLK TFCLK TDCREF TLOCK TPHASE
X-Ref Target - Figure 3
Description
Reference clock frequency range Reference clock rise time Reference clock fall time Reference clock duty cycle Clock recovery frequency acquisition time Clock recovery phase acquisition time
Conditions
All Speed Grades Min
62.5
Typ
- 200 200 50 - -
Max
650 - - 55 1 200
Units
MHz ps ps % ms s
20% - 80% 80% - 20% Transceiver PLL only Initial PLL lock Lock to data after PLL has locked to the reference clock
- - 45 - -
TRCLK
80%
20%
TFCLK
ds152_05_042109
Figure 3: Reference Clock Timing Parameters Table 22: GTX Transceiver User Clock Switching Characteristics(1)
Symbol
FTXOUT FRXREC TRX TRX2 TTX TTX2
Description
TXOUTCLK maximum frequency RXRECCLK maximum frequency RXUSRCLK maximum frequency
Conditions
Internal 20-bit data path Internal 16-bit data path Internal 20-bit data path Internal 16-bit data path 1 byte interface
Speed Grade -3
330 412.5 330 412.5 412.5(2) 376 406.25 206.25 412.5(3) 376 406.25 206.25
-2
330 412.5 330 412.5 412.5(2) 376 406.25 206.25 412.5(3) 376 406.25 206.25
-1
250 312.5 250 312.5 312.5 312.5 312.5 156.25 312.5 312.5 312.5 156.25
-1L
250 250 250 250 250 250 250 125 250 250 250 125
Units
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
RXUSRCLK2 maximum frequency TXUSRCLK maximum frequency
2 byte interface 4 byte interface 1 byte interface
TXUSRCLK2 maximum frequency
2 byte interface 4 byte interface
Notes:
1. 2. 3. Clocking must be implemented as described in the Virtex-6 FPGA GTX Transceivers User Guide. 406.25 MHz when the RX elastic buffer is bypassed. 406.25 MHz when the TX buffer is bypassed.
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 23: GTX Transceiver Transmitter Switching Characteristics
Symbol
FGTXTX TRTX TFTX TLLSKEW VTXOOBVDPP TTXOOBTRANSITION TJ6.5 DJ6.5 TJ5.0 DJ5.0 TJ4.25 DJ4.25 TJ3.75 DJ3.75 TJ3.125 DJ3.125 TJ3.125L DJ3.125L TJ2.5 DJ2.5 TJ1.25 DJ1.25 TJ600 DJ600 TJ480 DJ480 Notes:
1. 2. 3. 4. 5. 6. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to 12 consecutive transmitters (three fully populated GTX Quads). Using PLL_DIVSEL_FB = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations. All jitter values are based on a bit-error ratio of 1e-12. PLL frequency at 1.5625 GHz and OUTDIV = 1. PLL frequency at 2.5 GHz and OUTDIV = 2. PLL frequency at 2.5 GHz and OUTDIV = 4.
Description
Serial data rate range TX Rise time TX Fall time TX lane-to-lane skew(1) Electrical idle amplitude Electrical idle transition time Total Jitter(2)(3) Jitter(2)(3) Deterministic
Condition
20%-80% 80%-20%
Min
0.480 - - - - - - - - - - - - - - - - - - - - - - - - -
Typ
- 120 120 - - - - - - - - - - - - - - - - - - - - - - -
Max
FGTXMAX - - 350 15 75 0.33 0.17 0.33 0.15 0.33 0.14 0.34 0.16 0.2 0.1 0.35 0.16 0.20 0.08 0.15 0.06 0.1 0.03 0.1 0.03
Units
Gb/s ps ps ps mV ns UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI
6.5 Gb/s 5.0 Gb/s 4.25 Gb/s 3.75 Gb/s 3.125 Gb/s 3.125 Gb/s(4) 2.5 Gb/s(5) 1.25 Gb/s(6) 600 Mb/s 480 Mb/s
Total Jitter(2)(3) Deterministic Jitter(2)(3) Total Jitter(2)(3) Jitter(2)(3) Deterministic
Total Jitter(2)(3) Deterministic Jitter(2)(3) Total Jitter(2)(3) Jitter(2)(3) Deterministic
Total Jitter(2)(3) Deterministic Jitter(2)(3) Total Jitter(2)(3) Jitter(2)(3) Deterministic
Total Jitter(2)(3) Deterministic Jitter(2)(3) Total Jitter(2)(3) Jitter(2)(3) Deterministic
Total Jitter(2)(3) Deterministic Jitter(2)(3)
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 24: GTX Transceiver Receiver Switching Characteristics
Symbol
FGTXRX TRXELECIDLE RXOOBVDPP RXSST RXRL RXPPMTOL Serial data rate Time for RXELECIDLE to respond to loss or restoration of data OOB detect threshold peak-to-peak Receiver spread-spectrum tracking(1) Run length (CID) Data/REFCLK PPM offset tolerance Modulated @ 33 KHz Internal AC capacitor bypassed CDR CDR 2nd-order 2nd-order loop disabled loop enabled
Description
RX oversampler not enabled RX oversampler enabled
Min
0.600 0.480 -
Typ
- - 75
Max
FGTXMAX 0.600 -
Units
Gb/s Gb/s ns
60 -5000 - -200 -2000 0.44 0.44 0.44 0.44 0.45 0.45 0.5 0.5 0.4 0.4 0.70 0.70 0.1 0.1
- - - - - - - - - - - - - - - - - - -
150 0 512 200 2000 - - - - - - - - - - - - - -
mV ppm UI ppm ppm UI UI UI UI UI UI UI UI UI UI UI UI UI UI
SJ Jitter Tolerance(2)
JT_SJ6.5 JT_SJ5.0 JT_SJ4.25 JT_SJ3.75 JT_SJ3.125 JT_SJ3.125L JT_SJ2.5 JT_SJ1.25 JT_SJ600 JT_SJ480 Sinusoidal Jitter(3) Sinusoidal Sinusoidal Jitter(3) Jitter(3) 6.5 Gb/s 5.0 Gb/s 4.25 Gb/s 3.75 Gb/s 3.125 Gb/s 3.125 2.5 Gb/s(4) Gb/s(5)
Sinusoidal Jitter(3) Sinusoidal Jitter(3) Sinusoidal Sinusoidal Jitter(3) Jitter(3)
Sinusoidal Jitter(3) Sinusoidal Jitter(3) Sinusoidal Jitter(3)
1.25 Gb/s(6) 600 Mb/s 480 Mb/s 3.125 Gb/s 5.0 Gb/s 3.125 Gb/s 5.0 Gb/s
SJ Jitter Tolerance with Stressed
JT_TJSE3.125 JT_SJSE3.125 Notes:
1. 2. 3. 4. 5. 6. 7.
Eye(2)
Total Jitter with Stressed Eye(7) Sinusoidal Jitter with Stressed Eye(7)
Using PLL_RXDIVSEL_OUT = 1, 2, and 4. All jitter values are based on a bit error ratio of 1e-12. The frequency of the injected sinusoidal jitter is 80 MHz. PLL frequency at 1.5625 GHz and OUTDIV = 1. PLL frequency at 2.5 GHz and OUTDIV = 2. PLL frequency at 2.5 GHz and OUTDIV = 4. Composite jitter with RX equalizer enabled. DFE disabled.
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
GTH Transceiver Specifications
GTH Transceiver DC Characteristics
Table 25: Absolute Maximum Ratings for GTH Transceivers(1)
Symbol
MGTHAVCC MGTHAVCCRX MGTAVTT MGTHAVCCPLL VIN VMGTREFCLK Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Description
Analog supply voltage for the GTH transmitter, receiver, and common analog circuits Analog supply voltage for the GTH receiver circuits and common analog circuits Analog supply voltage for the GTH transmitter termination circuits Analog supply voltage for the GTH receiver and PLL circuits Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage Reference clock absolute input voltage
Min
-0.5 -0.5 -0.5 -0.5 -0.5 -0.5
Max
Units
V V V V V V
Table 26: Recommended Operating Conditions for GTH Transceivers (1)(2)
Symbol
MGTHAVCC MGTHAVCCRX MGTHAVTT MGTHAVCCPLL Notes:
1. 2. Each voltage listed requires the filter circuit described in Virtex-6 FPGA GTH Transceivers User Guide. Voltages are specified for the temperature range of Tj = -40C to +100C.
Description
Analog supply voltage for the GTH transmitter, receiver, and common analog circuits Analog supply voltage for the GTH receiver circuits and common analog circuits Analog supply voltage for the GTH transmitter termination circuits Analog supply voltage for the GTH receiver and PLL circuit
Min
1.075 1.075 1.140 1.710
Typ
1.1 1.1 1.2 1.8
Max
1.125 1.125 1.26 1.89
Units
V V V V
Table 27: GTH Transceiver Power Supply Sequencing (1)(2)
Symbol
THAVCC2HAVCCRX THAVCCRX2HAVCCPLL THAVCCRX2HAVTT Notes:
1. 2. MGTHAVCCRX must be powered simultaneously or within THAVCC2HAVCCRX of MGTHAVCC, but it must not precede MGTHAVCC. MGTHAVCC and MGTHAVCCRX must be powered before MGTHAVCCPLL and MGTHAVTT. This minimum time is defined by THAVCCRX2HAVCCPLL and THAVCCRX2HAVTT.
Description
Maximum time between powering MGTHAVCC to when MGTHAVCCRX must be powered. Minimum time between powering MGTHAVCCRX to when MGTHAVCCPLL can be powered. Minimum time between powering MGTHAVCCRX to when MGTHAVTT can be powered.
Min
0 10 10
Max
200 - -
Units
s s s
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics Figure 4 shows the timing parameters in Table 27.
X-Ref Target - Figure 4
MGTHAVCC (1.1V DC) THAVCC2HAVCCRX
MGTHAVCCRX (1.1V DC) THAVCCRX2HAVCCPLL
MGTHAVCCPLL (1.8V DC) THAVCCRX2HAVTT
MGTHAVTT (1.2V DC)
DS152_04_051110
Figure 4: GTH Transceiver Power Supply Power-On Sequencing Table 28: GTH Transceiver Supply Current (1)(2)
Symbol
IMGTHAVCC IMGTHAVCCRX IMGTHAVTT IMGTHAVCCPLL MGTRREF Notes:
1. 2. Typical values are specified at nominal voltage, 25C, with a 10.3125 Gb/s line rate. Values for currents other than the values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools.
Description
MGTHAVCC supply current for one GTH Quad (4 lanes) MGTHAVCCRX supply current for a GTH Quad (4 lanes) MGTHAVTT supply current for one GTH Quad (4 lanes) MGTHAVCCPLL supply current for one GTH Quad (4 lanes) Precision reference resistor for internal calibration termination
Min
Typ
Max
Units
mA mA mA mA
1000.0 1% tolerance
Table 29: GTH Transceiver Quiescent Supply Current(1)(2)(3)
Symbol
IMGTHAVCCQ IMGTHAVCCRXQ IMGTHAVTTQ IMGTHAVCCPLLQ Notes:
1. 2. 3. 4. Device powered and unconfigured. Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools. GTH transceiver quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of available GTH transceivers. Typical values are specified at nominal voltage, 25C.
Description
Quiescent MGTHAVCC Supply Current for one GTH Quad (4 lanes) Quiescent MGTHAVCCRX Supply Current for one GTH Quad (4 lanes) Quiescent MGTHAVTT Supply Current for one GTH Quad (4 lanes) Quiescent MGTHAVCCPLL Supply Current for one GTH Quad (4 lanes)
Typ(4)
Max
Units
mA mA mA mA
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
GTH Transceiver DC Input and Output Levels
Table 30 summarizes the DC output specifications of the GTH transceivers in Virtex-6 FPGAs. Consult the Virtex-6 FPGA GTH Transceivers User Guide for further details. Table 30: GTH Transceiver DC Specifications
Symbol
DVPPIN DVPPOUT RIN ROUT TOSKEW CEXT Notes:
1. 2. The output swing and preemphasis levels are programmable using the attributes discussed in the Virtex-6 FPGA GTH Transceivers User Guide and can result in values lower than reported in this table. Other values can be used as appropriate to conform to specific protocols and standards.
DC Parameter
Conditions
Min
Typ
Max
Units
mV mV
Differential peak-to-peak input voltage External AC coupled Differential peak-to-peak output voltage (1) Differential input resistance Differential output resistance Transmitter output pair (TXP and TXN) intra-pair skew Recommended external AC coupling capacitor(2) 100 Transmitter output swing is set to maximum setting 100 100
ps nF
Table 31 summarizes the DC specifications of the clock input of the GTH transceiver. Consult theVirtex-6 FPGA GTH Transceivers User Guide for further details. Table 31: GTH Transceiver Clock DC Input Level Specification
Symbol
VIDIFF RIN CEXT
DC Parameter
Differential peak-to-peak input voltage Differential input resistance Required external AC coupling capacitor
Conditions
600 MHz > 600 MHz
Min
500 600
Typ
Max
1600 1600
Units
mV mV nF
100 100
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
GTH Transceiver Switching Characteristics
Consult Virtex-6 FPGA GTH Transceivers User Guide for further information. Table 32: GTH Transceiver Maximum Data Rate and PLL Frequency Range
Symbol Description Conditions
PLL Output Divider = 1 PLL Output Divider = 4 PLL Output Divider = 1 PLL Output Divider = 4
Speed Grade -3
11.182 2.795 9.92 2.48 5.591 4.96
-2
11.182 2.795 9.92 2.48 5.591 4.96
-1
10.32 2.58 9.92 2.48 5.16 4.96
Units
Gb/s Gb/s Gb/s Gb/s GHz GHz
FGTHMAX FGTHMIN FGPLLMAX FGPLLMIN Notes:
1.
Maximum GTH transceiver data rate Minimum GTH transceiver data rate(1) Maximum GTH PLL frequency Minimum GTH PLL frequency
Lower data rates can be achieved using FPGA logic based oversampling designs.
Table 33: GTH Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol
FGTHDRPCLK
Description
GTHDRPCLK maximum frequency
Speed Grade -3
70
-2
70
-1
60
Units
MHz
Table 34: GTH Transceiver Reference Clock Switching Characteristics
Symbol Description Conditions
-1 speed grade -2 and -3 speed grades 20% - 80% 80% - 20% CLK Initial PLL lock Lock to data after PLL has locked to the reference clock 45
All Speed Grades Min
150 150 200 200 50 55
Typ
Max
623 670
Units
MHz MHz ps ps % ms s
FGCLK TRCLK TFCLK TDCREF TLOCK TPHASE
X-Ref Target - Figure 5
Reference clock frequency range Reference clock rise time Reference clock fall time Reference clock duty cycle Clock recovery frequency acquisition time Clock recovery phase acquisition time
TRCLK
80%
20%
TFCLK
ds152_05_042109
Figure 5: Reference Clock Timing Parameters
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 35: GTH Transceiver User Clock Switching Characteristics (1)
Symbol
FTXOUT FRXOUT
Description
TXUSERCLKOUT maximum frequency RXUSERCLKOUT maximum frequency
Conditions
Speed Grade -3
350 350
-2
350 350 350 280 350 280 175 140 170 350 280 350 280 175 140 170
-1
323 323 323 258 323 258 162 129 157 323 258 323 258 162 129 157
Units
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
16-bit data path 20-bit data path 32-bit data path FTXIN TXUSERCLKIN maximum frequency 40-bit data path 64-bit data path 80-bit data path 64B/66B-bit data path 16-bit data path 20-bit data path 32-bit data path FRXIN RXUSERCLKIN maximum frequency 40-bit data path 64-bit data path 80-bit data path 64B/66B-bit data path Notes:
1.
350 280 350 280 175 140 170 350 280 350 280 175 140 170
Clocking must be implemented as described in the Virtex-6 FPGA GTH Transceivers User Guide.
Table 36: GTH Transceiver Transmitter Switching Characteristics
Symbol
TRTX TFTX TLLSKEW TX Rise time TX Fall time
Description
Condition
20%-80% 80%-20% within one GTH Quad across multiple GTH Quads 11.181 Gb/s 10.3125 Gb/s 9.953 Gb/s 2.667 Gb/s 2.488 Gb/s
Min
Typ
Max
Units
ps ps ps ps
TX lane-to-lane skew
Transmitter Output Jitter(1)(2)
TJ11.18 DJ11.18 TJ10.3125 DJ10.3125 TJ9.953 DJ9.953 TJ2.667 DJ2.667 TJ2.488 DJ2.488 Notes:
1. 2. These values are NOT intended for protocol specific compliance determinations. All jitter values are based on a bit-error ratio of 1e-12.
Total Jitter Deterministic Jitter Total Jitter Deterministic Jitter Total Jitter Deterministic Jitter Total Jitter Deterministic Jitter Total Jitter Deterministic Jitter
UI UI UI UI UI UI UI UI UI UI
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 37: GTH Transceiver Receiver Switching Characteristics
Symbol
RXRL RXPPMTOL Run length (CID) Data/REFCLK PPM offset tolerance Sinusoidal Jitter Sinusoidal Jitter Sinusoidal Jitter Sinusoidal Jitter Sinusoidal Jitter 11.18 Gb/s 10.32 Gb/s 9.95 Gb/s 2.667 Gb/s 2.48 Gb/s -200 200
Description
Min
Typ
Max
Units
UI ppm UI UI UI UI UI
SJ Jitter
Tolerance(1)(2)(3)
JT_SJ11.18 JT_SJ10.32 JT_SJ9.95 JT_SJ2.667 JT_SJ2.48 Notes:
1. 2. 3.
These values are NOT intended for protocol specific compliance determinations. All jitter values are based on a bit error ratio of 1e-12. The frequency of the injected sinusoidal jitter is 80 MHz.
Ethernet MAC Switching Characteristics
Consult Virtex-6 FPGA Embedded Tri-mode Ethernet MAC User Guide for further information. Table 38: Maximum Ethernet MAC Performance
Symbol
FTEMACCLIENT
Description
Client interface maximum frequency
Conditions
10 Mb/s - 8-bit width 100 Mb/s - 8-bit width 1000 Mb/s - 8-bit width 1000 Mb/s - 16-bit width 2000 Mb/s - 16-bit width 2500 Mb/s - 16-bit width
Speed Grade -3
2.5(1) 25(2) 125 62.5 125 156.25 2.5 25 125 250 312.5
-2
2.5(1) 25(2) 125 62.5 125 156.25 2.5 25 125 250 312.5
-1
2.5(1) 25(2) 125 62.5 125 156.25 2.5 25 125 250 312.5
-1L
2.5(1) 25(2) 125 62.5 N/A N/A 2.5 25 125 N/A N/A
Units
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
FTEMACPHY
Physical interface maximum frequency
10 Mb/s - 4-bit width 100 Mb/s - 4-bit width 1000 Mb/s - 8-bit width 2000 Mb/s - 8-bit width 2500 Mb/s - 8-bit width
Notes:
1. 2. When not using clock enable, the FMAX is lowered to 1.25 MHz. When not using clock enable, the FMAX is lowered to 12.5 MHz.
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Integrated Interface Block for PCI Express Designs Switching Characteristics
More information and documentation on solutions for PCI Express designs can be found at: http://www.xilinx.com/technology/protocols/pciexpress.htm Table 39: Maximum Performance for PCI Express Designs
Symbol
FPIPECLK FUSERCLK FDRPCLK
Description
Pipe clock maximum frequency User clock maximum frequency DRP clock maximum frequency
Speed Grade -3
250 500 250
-2
250 500 250
-1
250 250 250
-1L
250 250 250
Units
MHz MHz MHz
System Monitor Analog-to-Digital Converter Specification
Table 40: Analog-to-Digital Specifications
Parameter Symbol Comments/Conditions Min Typ Max Units
AVDD = 2.5V 5%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 5.2 MHz, Tj = -40C to 100C, Typical values at Tj=+35C DC Accuracy: All external input channels. Both unipolar and bipolar modes. Resolution Integral Nonlinearity Differential Nonlinearity Unipolar Offset Error (1) Bipolar Offset Error Gain Error
(1) (1)
10 INL DNL No missing codes (TMIN to TMAX) Guaranteed Monotonic Uncalibrated Uncalibrated measured in bipolar mode Uncalibrated - External Reference Uncalibrated - Internal Reference - - - - - - - - - - - - -
- - - 2 2 0.2 2 0.2 2 10 20 1 0.01 70
- 1 0.9 30 30 2 - 2 - - - 2 - -
Bits LSBs LSBs LSBs LSBs % % % % LSBs LSBs LSBs LSB/C dB
Bipolar Gain Error
Uncalibrated - External Reference Uncalibrated - Internal Reference
Total Unadjusted Error (Uncalibrated)
TUE
Deviation from ideal transfer function. External 1.25V reference Deviation from ideal transfer function. Internal reference
Total Unadjusted Error (Calibrated) Calibrated Gain Temperature Coefficient DC Common-Mode Reject Conversion Rate(2) Conversion Time - Continuous Conversion Time - Event T/H Acquisition Time DRP Clock Frequency ADC Clock Frequency CLK Duty cycle
TUE
Deviation from ideal transfer function. External 1.25V reference Variation of FS code with temperature
CMRRDC
VN = VCM = 0.5V 0.5V, VP - VN = 100mV Number of CLK cycles Number of CLK cycles Number of CLK cycles DRP clock frequency Derived from DCLK
tCONV tCONV tACQ DCLK ADCCLK
26 - 4 8 1 40
- - - - - -
32 21 - 80 5.2 60 MHz MHz %
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics Table 40: Analog-to-Digital Specifications (Cont'd)
Parameter
Analog Inputs(3) Dedicated Analog Inputs Input Voltage Range VP - VN Unipolar Operation Bipolar Operation Unipolar Common Mode Range (FS input) Bipolar Common Mode Range (FS input) Bandwidth Auxiliary Analog Inputs Input Voltage Range VAUXP[0] /VAUXN[0] to VAUXP[15] /VAUXN[15] Tj = -40C to 100C Unipolar Operation Bipolar Operation Unipolar Common Mode Range (FS input) Bipolar Common Mode Range (FS input) Bandwidth Input Leakage Current Input Capacitance On-chip Supply Monitor Error VCCINT and VCCAUX with calibration enabled. External 1.25V reference Tj = -40C to 125C. VCCINT and VCCAUX with calibration enabled. Internal reference Tj = -40C to 100C. On-chip Temperature Monitor Error Tj = -40C to +125C with calibration enabled. External 1.25V reference. Tj = -40C to +100C with calibration enabled. Internal reference. External Reference Inputs(4) Positive Reference Input Voltage Range Negative Reference Input Voltage Range Input current Power Requirements Analog Power Supply Analog Supply Current Notes:
1. 2. 3. 4. Offset errors are removed by enabling the System Monitor automatic gain calibration feature. See "System Monitor Timing" in the Virtex-6 FPGA System Monitor User Guide See "Analog Inputs" in the Virtex-6 FPGA System Monitor User Guide for a detailed description. Any variation in the reference voltage from the nominal VREFP = 1.25V and VREFN = 0V will result is a deviation from the ideal transfer function.This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing reference to vary by 4% is permitted.
Symbol
Comments/Conditions
Min
Typ
Max
Units
0 -0.5 0 +0.5 - 0 -0.5 0 +0.5 - - - - - - -
- - - - 20 - - - - 10 1.0 10 - 2 - 5
1 +0.5 +0.5 +0.6 - 1 +0.5 +0.5 +0.6 - - - 1.0 - 4 -
Volts
MHz Volts
kHz A pF % Reading % Reading C C
A/D not converting, ADCCLK stopped
VREFP VREFN IREF AVDD AIDD
Measured Relative to VREFN Measured Relative to AGND ADCCLK = 5.2 MHz
1.20 -50 -
1.25 0 -
1.30 100 100
Volts mV A
Measured Relative to AVSS ADCCLK = 5.2 MHz
2.375 -
2.5 -
2.625 12
Volts mA
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in Virtex-6 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as the Switching Characteristics, page 24. Table 41: Interface Performances
Description
Networking Applications SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8) DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 10) SDR LVDS receiver DDR LVDS receiver (SFI-4.1)(1) (SPI-4.2)(1) Interfaces(2)(3) 800 Mb/s 1066 Mb/s 400 MHz 500 MHz 800 Mb/s 1066 Mb/s 350 MHz 400 MHz 800 Mb/s 800 Mb/s 300 MHz 350 MHz 606 Mb/s 606 Mb/s - - 710 Mb/s 1.4 Gb/s 710 Mb/s 1.4 Gb/s 710 Mb/s 1.3 Gb/s 710 Mb/s 1.3 Gb/s 650 Mb/s 1.25 Gb/s 650 Mb/s 1.0 Gb/s 585 Mb/s 1.1 Gb/s 585 Mb/s 0.9 Gb/s
Speed Grade -3 -2 -1 -1L
Maximum Physical Interface (PHY) Rate for Memory DDR2 DDR3 QDR II + SRAM RLDRAM II Notes:
1. 2. 3.
LVDS receivers are typically bounded with certain applications where specific DPA algorithms dominate deterministic performance. Verified on Xilinx memory characterization platforms designed according to the guidelines in theVirtex-6 FPGA Memory Interface Solutions User Guide. Consult theVirtex-6 FPGA Memory Interface Solutions Data Sheet for performance and feature information on memory interface cores (controller plus PHY).
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Switching Characteristics
All values represented in this data sheet are based on these speed specifications: v1.10 for -3, -2, and -1; and v1.07 for -1L. Switching characteristics are specified on a per-speedgrade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: Advance These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some underreporting might still occur. Preliminary These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Production These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. All specifications are always representative of worst-case supply voltage and junction temperature conditions. Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 42 correlates the current status of each Virtex-6 device on a per speed grade basis. Table 42: Virtex-6 Device Speed Grade Designations
Device
XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T -3, -2, -1 -3, -2, -1 -2, -1 -3, -2, -1
Speed Grade Designations Advance Preliminary Production
-3, -2, -1, -1L -3, -2, -1, -1L -3, -2, -1, -1L -3, -2, -1, -1L -3, -2, -1, -1L -2, -1, -1L -2, -1, -1L -3, -2, -1, -1L -2, -1, -1L
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex-6 devices.
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Production Silicon and ISE Software Status
In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases. Table 43 lists the production released Virtex-6 family member, speed grade, and the minimum corresponding supported speed specification version and ISE software revisions. The ISE(R) software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid.
Table 43: Virtex-6 Device Production Software and Speed Specification Release
Device
XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T Notes:
1. Blank entries indicate a device and/or speed grade in advance or preliminary status.
Speed Grade Designations -3 -2
ISE 12.2 v1.08 ISE 12.1 v1.06 ISE 12.1 v1.06 ISE 12.1 v1.06 ISE 11.5 v1.05 ISE 12.1 v1.06 ISE 11.4.1 v1.04 ISE 12.2 v1.08 N/A N/A ISE 12.2 v1.08 N/A ISE 12.2 v1.07 ISE 12.2 v1.08 ISE 12.1 v1.06 ISE 12.2 v1.08 ISE 11.5 v1.05 ISE 12.1 v1.06 ISE 11.4.1 v1.04
-1
-1L
ISE 12.3 v1.07 Patch ISE 12.2 v1.05 ISE 12.2 v1.04 ISE 12.2 v1.04 ISE 12.2 v1.04 ISE 12.2 v1.04 ISE 12.3 v1.07 Patch ISE 12.3 v1.07 Patch ISE 12.3 v1.07 Patch N/A N/A N/A
N/A
N/A
IOB Pad Input/Output/3-State Switching Characteristics
Table 44 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer. TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer. Table 44: IOB Switching Characteristics
TIOPI I/O Standard -3
LVDS_25 LVDSEXT_25 HT_25 0.85 0.85 0.85
TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. Table 45 summarizes the value of TIOTPHZ. TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state).
TIOOP Speed Grade -1L
1.08 1.08 1.08
TIOTP
Speed Grade
Speed Grade -2
0.94 0.94 0.94
Units -1L
1.62 1.73 1.69 ns ns ns
-1
1.09 1.09 1.09
-3
1.45 1.53 1.51
-2
1.54 1.65 1.62
-1
1.68 1.84 1.78
-1L
1.62 1.73 1.69
-3
1.45 1.53 1.51
-2
1.54 1.65 1.62
-1
1.68 1.84 1.78
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics Table 44: IOB Switching Characteristics (Cont'd)
TIOPI I/O Standard -3
BLVDS_25 RSDS_25 (point to point) HSTL_I HSTL_II HSTL_III HSTL_I_18 HSTL_II_18 HSTL_III_18 SSTL2_I SSTL2_II SSTL15 LVCMOS25, Slow, 2 mA LVCMOS25, Slow, 4 mA LVCMOS25, Slow, 6 mA LVCMOS25, Slow, 8 mA LVCMOS25, Slow, 12 mA LVCMOS25, Slow, 16 mA LVCMOS25, Slow, 24 mA LVCMOS25, Fast, 2 mA LVCMOS25, Fast, 4 mA LVCMOS25, Fast, 6 mA LVCMOS25, Fast, 8 mA LVCMOS25, Fast, 12 mA LVCMOS25, Fast, 16 mA LVCMOS25, Fast, 24 mA LVCMOS18, Slow, 2 mA LVCMOS18, Slow, 4 mA LVCMOS18, Slow, 6 mA LVCMOS18, Slow, 8 mA LVCMOS18, Slow, 12 mA LVCMOS18, Slow, 16 mA LVCMOS18, Fast, 2 mA LVCMOS18, Fast, 4 mA LVCMOS18, Fast, 6 mA LVCMOS18, Fast, 8 mA LVCMOS18, Fast, 12 mA LVCMOS18, Fast, 16 mA LVCMOS15, Slow, 2 mA 0.85 0.85 0.81 0.81 0.81 0.81 0.81 0.81 0.81 0.81 0.81 0.51 0.51 0.51 0.51 0.51 0.51 0.51 0.51 0.51 0.51 0.51 0.51 0.51 0.51 0.55 0.55 0.55 0.55 0.55 0.55 0.55 0.55 0.55 0.55 0.55 0.55 0.64
TIOOP Speed Grade -1L
1.08 1.08 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.85
TIOTP
Speed Grade
Speed Grade -2
0.94 0.94 0.91 0.91 0.91 0.91 0.91 0.91 0.91 0.91 0.91 0.57 0.57 0.57 0.57 0.57 0.57 0.57 0.57 0.57 0.57 0.57 0.57 0.57 0.57 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.73
Units -1L
1.65 1.62 1.71 1.72 1.69 1.72 1.78 1.69 1.74 1.71 1.69 5.63 3.65 2.95 2.59 2.10 2.21 1.98 5.62 3.65 2.88 2.53 2.03 2.08 1.96 4.30 2.94 2.47 2.24 2.10 2.04 4.08 2.74 2.32 2.14 1.88 1.88 3.91 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-1
1.09 1.09 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.85
-3
1.39 1.45 1.45 1.44 1.42 1.47 1.50 1.42 1.49 1.42 1.42 5.09 3.30 2.62 2.21 1.80 1.89 1.68 5.12 3.28 2.56 2.11 1.74 1.77 1.66 4.21 2.79 2.30 2.01 1.88 1.84 4.00 2.62 2.15 1.90 1.69 1.63 3.43
-2
1.50 1.54 1.56 1.56 1.54 1.58 1.62 1.54 1.60 1.54 1.54 5.46 3.49 2.81 2.41 1.95 2.05 1.82 5.49 3.50 2.73 2.33 1.88 1.92 1.79 4.47 2.96 2.43 2.11 1.99 1.95 4.23 2.76 2.28 1.99 1.80 1.74 3.77
-1
1.67 1.68 1.73 1.74 1.71 1.75 1.81 1.71 1.77 1.72 1.71 6.01 3.79 3.08 2.72 2.17 2.29 2.02 6.04 3.82 2.99 2.65 2.08 2.13 1.99 4.87 3.21 2.64 2.27 2.15 2.11 4.57 2.97 2.46 2.13 1.97 1.91 4.29
-1L
1.65 1.62 1.71 1.72 1.69 1.72 1.78 1.69 1.74 1.71 1.69 5.63 3.65 2.95 2.59 2.10 2.21 1.98 5.62 3.65 2.88 2.53 2.03 2.08 1.96 4.30 2.94 2.47 2.24 2.10 2.04 4.08 2.74 2.32 2.14 1.88 1.88 3.91
-3
1.39 1.45 1.45 1.44 1.42 1.47 1.50 1.42 1.49 1.42 1.42 5.09 3.30 2.62 2.21 1.80 1.89 1.68 5.12 3.28 2.56 2.11 1.74 1.77 1.66 4.21 2.79 2.30 2.01 1.88 1.84 4.00 2.62 2.15 1.90 1.69 1.63 3.43
-2
1.50 1.54 1.56 1.56 1.54 1.58 1.62 1.54 1.60 1.54 1.54 5.46 3.49 2.81 2.41 1.95 2.05 1.82 5.49 3.50 2.73 2.33 1.88 1.92 1.79 4.47 2.96 2.43 2.11 1.99 1.95 4.23 2.76 2.28 1.99 1.80 1.74 3.77
-1
1.67 1.68 1.73 1.74 1.71 1.75 1.81 1.71 1.77 1.72 1.71 6.01 3.79 3.08 2.72 2.17 2.29 2.02 6.04 3.82 2.99 2.65 2.08 2.13 1.99 4.87 3.21 2.64 2.27 2.15 2.11 4.57 2.97 2.46 2.13 1.97 1.91 4.29
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics Table 44: IOB Switching Characteristics (Cont'd)
TIOPI I/O Standard -3
LVCMOS15, Slow, 4 mA LVCMOS15, Slow, 6 mA LVCMOS15, Slow, 8 mA LVCMOS15, Slow, 12 mA LVCMOS15, Slow, 16 mA LVCMOS15, Fast, 2 mA LVCMOS15, Fast, 4 mA LVCMOS15, Fast, 6 mA LVCMOS15, Fast, 8 mA LVCMOS15, Fast, 12 mA LVCMOS15, Fast, 16 mA LVCMOS12, Slow, 2 mA LVCMOS12, Slow, 4 mA LVCMOS12, Slow, 6 mA LVCMOS12, Slow, 8 mA LVCMOS12, Fast, 2 mA LVCMOS12, Fast, 4 mA LVCMOS12, Fast, 6 mA LVCMOS12, Fast, 8 mA LVDCI_25 LVDCI_18 LVDCI_15 LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2_15 LVPECL_25 HSTL_I_12 HSTL_I_DCI HSTL_II_DCI HSTL_II_T_DCI HSTL_III_DCI HSTL_I_DCI_18 HSTL_II_DCI_18 HSTL_II _T_DCI_18 HSTL_III_DCI_18 DIFF_HSTL_I_18 DIFF_HSTL_I_DCI_18 DIFF_HSTL_I 0.64 0.64 0.64 0.64 0.64 0.64 0.64 0.64 0.64 0.64 0.64 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.51 0.55 0.64 0.51 0.55 0.64 0.85 0.81 0.81 0.81 0.81 0.81 0.81 0.81 0.81 0.81 0.85 0.85 0.85
TIOOP Speed Grade -1L
0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.95 0.95 0.95 0.95 0.95 0.95 0.95 0.95 0.70 0.73 0.85 0.70 0.73 0.85 1.08 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.08 1.08 1.08
TIOTP
Speed Grade
Speed Grade -2
0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.81 0.81 0.81 0.81 0.81 0.81 0.81 0.81 0.57 0.61 0.73 0.57 0.61 0.73 0.94 0.91 0.91 0.91 0.91 0.91 0.91 0.91 0.91 0.91 0.94 0.94 0.94
Units -1L
2.93 2.50 2.24 2.07 1.98 3.91 2.66 2.16 2.04 1.90 1.92 3.54 2.79 2.26 2.17 3.11 2.31 2.05 1.98 2.26 2.38 2.18 2.00 1.98 1.98 1.64 1.74 1.64 1.66 1.64 1.61 1.66 1.59 1.66 1.67 1.72 1.66 1.71 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-1
0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.93 0.93 0.93 0.93 0.93 0.93 0.93 0.93 0.66 0.71 0.85 0.66 0.71 0.85 1.09 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.09 1.09 1.09
-3
2.58 2.08 1.81 1.76 1.69 3.44 2.37 1.80 1.76 1.64 1.62 3.14 2.43 1.92 1.87 2.71 1.93 1.75 1.69 2.05 2.07 1.85 1.71 1.69 1.68 1.38 1.48 1.40 1.37 1.40 1.34 1.42 1.36 1.42 1.43 1.47 1.42 1.45
-2
2.79 2.32 1.98 1.91 1.83 3.77 2.53 2.05 1.90 1.77 1.76 3.39 2.63 2.11 2.02 2.98 2.16 1.89 1.82 2.14 2.23 2.01 1.83 1.81 1.77 1.49 1.60 1.50 1.49 1.50 1.45 1.53 1.46 1.53 1.54 1.58 1.53 1.56
-1
3.10 2.68 2.23 2.13 2.04 4.28 2.78 2.42 2.11 1.97 1.96 3.75 2.93 2.41 2.25 3.39 2.51 2.11 2.02 2.26 2.47 2.24 2.01 2.00 1.91 1.65 1.78 1.66 1.68 1.66 1.62 1.68 1.62 1.68 1.69 1.75 1.68 1.73
-1L
2.93 2.50 2.24 2.07 1.98 3.91 2.66 2.16 2.04 1.90 1.92 3.54 2.79 2.26 2.17 3.11 2.31 2.05 1.98 2.26 2.38 2.18 2.00 1.98 1.98 1.64 1.74 1.64 1.66 1.64 1.61 1.66 1.59 1.66 1.67 1.72 1.66 1.71
-3
2.58 2.08 1.81 1.76 1.69 3.44 2.37 1.80 1.76 1.64 1.62 3.14 2.43 1.92 1.87 2.71 1.93 1.75 1.69 2.05 2.07 1.85 1.71 1.69 1.68 1.38 1.48 1.40 1.37 1.40 1.34 1.42 1.36 1.42 1.43 1.47 1.42 1.45
-2
2.79 2.32 1.98 1.91 1.83 3.77 2.53 2.05 1.90 1.77 1.76 3.39 2.63 2.11 2.02 2.98 2.16 1.89 1.82 2.14 2.23 2.01 1.83 1.81 1.77 1.49 1.60 1.50 1.49 1.50 1.45 1.53 1.46 1.53 1.54 1.58 1.53 1.56
-1
3.10 2.68 2.23 2.13 2.04 4.28 2.78 2.42 2.11 1.97 1.96 3.75 2.93 2.41 2.25 3.39 2.51 2.11 2.02 2.26 2.47 2.24 2.01 2.00 1.91 1.65 1.78 1.66 1.68 1.66 1.62 1.68 1.62 1.68 1.69 1.75 1.68 1.73
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics Table 44: IOB Switching Characteristics (Cont'd)
TIOPI I/O Standard -3
DIFF_HSTL_I_DCI DIFF_HSTL_II_18 DIFF_HSTL_II_DCI_18 DIFF_HSTL_II _T_DCI_18 DIFF_HSTL_II DIFF_HSTL_II_DCI SSTL2_I_DCI SSTL2_II_DCI SSTL2_II_T_DCI SSTL18_I SSTL18_II SSTL18_I_DCI SSTL18_II_DCI SSTL18_II_T_DCI SSTL15_T_DCI SSTL15_DCI DIFF_SSTL2_I DIFF_SSTL2_I_DCI DIFF_SSTL2_II DIFF_SSTL2_II_DCI DIFF_SSTL2_II_T_DCI DIFF_SSTL18_I DIFF_SSTL18_I_DCI DIFF_SSTL18_II DIFF_SSTL18_II_DCI DIFF_SSTL18_II_T_DCI DIFF_SSTL15 DIFF_SSTL15_DCI DIFF_SSTL15_T_DCI 0.85 0.85 0.85 0.85 0.85 0.85 0.81 0.81 0.81 0.81 0.81 0.81 0.81 0.81 0.81 0.81 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.81 0.81 0.81
TIOOP Speed Grade -1L
1.08 1.08 1.08 1.08 1.08 1.08 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.08 1.08 1.08 1.08 1.08 1.08 1.08 1.08 1.08 1.08 1.06 1.06 1.06
TIOTP
Speed Grade
Speed Grade -2
0.94 0.94 0.94 0.94 0.94 0.94 0.91 0.91 0.91 0.91 0.91 0.91 0.91 0.91 0.91 0.91 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.91 0.91 0.91
Units -1L
1.64 1.78 1.59 1.66 1.72 1.66 1.68 1.69 1.68 1.73 1.66 1.65 1.62 1.65 1.66 1.66 1.74 1.68 1.71 1.69 1.68 1.73 1.65 1.66 1.62 1.65 1.69 1.66 1.66 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-1
1.09 1.09 1.09 1.09 1.09 1.09 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.09 1.09 1.09 1.09 1.09 1.09 1.09 1.09 1.09 1.09 1.06 1.06 1.06
-3
1.40 1.50 1.36 1.42 1.44 1.37 1.42 1.39 1.42 1.47 1.39 1.40 1.36 1.40 1.41 1.41 1.49 1.42 1.42 1.39 1.42 1.47 1.40 1.39 1.36 1.40 1.42 1.41 1.41
-2
1.50 1.62 1.46 1.53 1.56 1.49 1.53 1.50 1.53 1.58 1.50 1.51 1.47 1.51 1.52 1.52 1.60 1.53 1.54 1.50 1.53 1.58 1.51 1.50 1.47 1.51 1.54 1.52 1.52
-1
1.66 1.81 1.62 1.68 1.74 1.68 1.70 1.67 1.70 1.75 1.67 1.67 1.63 1.67 1.68 1.68 1.77 1.70 1.72 1.67 1.70 1.75 1.67 1.67 1.63 1.67 1.71 1.68 1.68
-1L
1.64 1.78 1.59 1.66 1.72 1.66 1.68 1.69 1.68 1.73 1.66 1.65 1.62 1.65 1.66 1.66 1.74 1.68 1.71 1.69 1.68 1.73 1.65 1.66 1.62 1.65 1.69 1.66 1.66
-3
1.40 1.50 1.36 1.42 1.44 1.37 1.42 1.39 1.42 1.47 1.39 1.40 1.36 1.40 1.41 1.41 1.49 1.42 1.42 1.39 1.42 1.47 1.40 1.39 1.36 1.40 1.42 1.41 1.41
-2
1.50 1.62 1.46 1.53 1.56 1.49 1.53 1.50 1.53 1.58 1.50 1.51 1.47 1.51 1.52 1.52 1.60 1.53 1.54 1.50 1.53 1.58 1.51 1.50 1.47 1.51 1.54 1.52 1.52
-1
1.66 1.81 1.62 1.68 1.74 1.68 1.70 1.67 1.70 1.75 1.67 1.67 1.63 1.67 1.68 1.68 1.77 1.70 1.72 1.67 1.70 1.75 1.67 1.67 1.63 1.67 1.71 1.68 1.68
Table 45: IOB 3-state ON Output Switching Characteristics (TIOTPHZ)
Symbol
TIOTPHZ
Description
T input to Pad high-impedance
Speed Grade -3
0.86
-2
0.92
-1
0.99
-1L
0.99
Units
ns
DS152 (v2.10) October18, 2010 Advance Product Specification
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 46 shows the test setup parameters used for measuring input delay. Table 46: Input Delay Measurement Methodology
Description
LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, 1.5V HSTL (High-Speed Transceiver Logic), Class I & II HSTL, Class III HSTL, Class I & II, 1.8V HSTL, Class III 1.8V SSTL (Stub Terminated Transceiver Logic), Class I & II, 3.3V SSTL, Class I & II, 2.5V SSTL, Class I & II, 1.8V LVDS (Low-Voltage Differential Signaling), 2.5V LVDSEXT (LVDS Extended Mode), 2.5V HT (HyperTransport), 2.5V Notes:
1. The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other DCI standards are the same for the corresponding non-DCI standards. Input waveform switches between VLand VH. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical. Input voltage level from which measurement starts. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 6. The value given is the differential input voltage.
I/O Standard Attribute LVCMOS25 LVCMOS18 LVCMOS15 HSTL_I, HSTL_II HSTL_III HSTL_I_18, HSTL_II_18 HSTL_III_18 SSTL3_I, SSTL3_II SSTL2_I, SSTL2_II SSTL18_I, SSTL18_II LVDS_25 LVDSEXT_25 LDT_25
VL (1)(2)
0 0 0 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 1.00 VREF - 0.75 VREF - 0.5 1.2 - 0.125 1.2 - 0.125 0.6 - 0.125
VH(1)(2)
2.5 1.8 1.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 1.00 VREF + 0.75 VREF + 0.5 1.2 + 0.125 1.2 + 0.125 0.6 + 0.125
VMEAS
(1)(4)(5)
VREF
(1)(3)(5)
1.25 0.9 0.75 VREF VREF VREF VREF VREF VREF VREF 0(6) 0(6) 0(6)
- - - 0.75 0.90 0.90 1.08 1.5 1.25 0.90 - - -
2. 3. 4. 5. 6.
DS152 (v2.10) October18, 2010 Advance Product Specification
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Output Delay Measurements
Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pF) across approximately 4" of FR4 microstrip trace. Standard termination was used for all testing. The propagation delay of the 4" trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in Figure 6 and Figure 7.
X-Ref Target - Figure 6
X-Ref Target - Figure 7
FPGA Output
+ CREF RREF VMEAS -
ds152_07_042109
VREF
Figure 7: Differential Test Setup Measurements and test conditions are reflected in the IBIS models except where the IBIS format precludes it. Parameters VREF , RREF , CREF , and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using the following method: 1. Simulate the output driver of choice into the generalized test setup, using values from Table 47. 2. Record the time to VMEAS .
ds152_06_042109
FPGA Output
RREF
VMEAS
(voltage level when taking delay measurement)
CREF
(probe capacitance)
Figure 6: Single Ended Test Setup
3. Simulate the output driver of choice into the actual PCB trace and load, using the appropriate IBIS model or capacitance value to represent the load. 4. Record the time to VMEAS . 5. Compare the results of steps 2 and 4. The increase or decrease in delay yields the actual propagation delay of the PCB trace.
Table 47: Output Delay Measurement Methodology
Description
LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, 1.5V LVCMOS, 1.2V HSTL (High-Speed Transceiver Logic), Class I HSTL, Class II HSTL, Class III HSTL, Class I, 1.8V HSTL, Class II, 1.8V HSTL, Class III, 1.8V SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL, Class II, 1.8V SSTL, Class I, 2.5V SSTL, Class II, 2.5V LVDS (Low-Voltage Differential Signaling), 2.5V LVDSEXT (LVDS Extended Mode), 2.5V BLVDS (Bus LVDS), 2.5V
I/O Standard Attribute
LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 HSTL_I HSTL_II HSTL_III HSTL_I_18 HSTL_II_18 HSTL_III_18 SSTL18_I SSTL18_II SSTL2_I SSTL2_II LVDS_25 LVDS_25 BLVDS_25
RREF ()
1M 1M 1M 1M 50 25 50 50 25 50 50 25 50 25 100 100 100
CREF(1) (pF)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VMEAS (V)
1.25 0.9 0.75 0.75 VREF VREF 0.9 VREF VREF 1.1 VREF VREF VREF VREF 0(2) 0(2) 0(2)
VREF (V)
0 0 0 0 0.75 0.75 1.5 0.9 0.9 1.8 0.9 0.9 1.25 1.25 1.2 1.2 0
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics Table 47: Output Delay Measurement Methodology (Cont'd)
Description
HT (HyperTransport), 2.5V LVPECL (Low-Voltage Positive Emitter-Coupled Logic), 2.5V LVDCI/HSLVDCI, 2.5V LVDCI/HSLVDCI, 1.8V LVDCI/HSLVDCI, 1.5V LDT_25 LVPECL_25 LVDCI_25, HSLVDCI_25 LVDCI_18, HSLVDCI_18 LVDCI_15, HSLVDCI_15
I/O Standard Attribute
RREF ()
100 100 1M 1M 1M 50 50 50 50 50 50
CREF(1) (pF)
0 0 0 0 0 0 0 0 0 0 0
VMEAS (V)
0(2) 0(2) 1.25 0.9 0.75 VREF 0.9 VREF 1.1 VREF VREF
VREF (V)
0.6 0 0 0 0 0.75 1.5 0.9 1.8 0.9 1.25
HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI HSTL, Class III, with DCI HSTL, Class I & II, 1.8V, with DCI HSTL, Class III, 1.8V, with DCI HSTL_III_DCI HSTL_I_DCI_18, HSTL_II_DCI_18 HSTL_III_DCI_18
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI SSTL, Class I & II, 2.5V, with DCI Notes:
1. 2. CREF is the capacitance of the probe, nominally 0 pF. The value given is the differential output voltage.
SSTL2_I_DCI, SSTL2_II_DCI
Input/Output Logic Switching Characteristics
Table 48: ILOGIC Switching Characteristics
Symbol
Setup/Hold TICE1CK/TICKCE1 TISRCK/TICKSR TIDOCK/TIOCKD TIDOCKD/TIOCKDD Combinatorial TIDI TIDID Sequential Delays TIDLO TIDLOD TICKQ TRQ_ILOGIC TGSRQ_ILOGIC Set/Reset TRPW_ILOGIC Minimum Pulse Width, SR inputs 0.78 0.95 1.20 1.30 ns, Min D pin to Q1 pin using flip-flop as a latch without Delay DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY) CLK to Q outputs SR pin to OQ/TQ out Global Set/Reset to Q outputs 0.48 0.52 0.54 0.85 7.60 0.54 0.58 0.61 0.97 7.60 0.64 0.68 0.70 1.15 10.51 0.73 0.78 0.93 1.32 10.51 ns ns ns ns ns D pin to O pin propagation delay, no Delay DDLY pin to O pin propagation delay (using IODELAY) 0.15 0.19 0.17 0.22 0.20 0.25 0.23 0.28 ns ns CE1 pin Setup/Hold with respect to CLK SR pin Setup/Hold with respect to CLK D pin Setup/Hold with respect to CLK without Delay DDLY pin Setup/Hold with respect to CLK (using IODELAY) 0.21/ 0.03 0.66/ -0.08 0.07/ 0.41 0.10/ 0.32 0.25/ 0.04 0.78/ -0.08 0.08/ 0.46 0.12/ 0.36 0.27/ 0.04 0.96/ -0.08 0.10/ 0.54 0.14/ 0.42 0.31/ 0.05 1.09/ -0.11 0.11/ 0.64 0.16/ 0.50 ns ns ns ns
Description
Speed Grade -3 -2 -1 -1L
Units
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 49: OLOGIC Switching Characteristics
Symbol
Setup/Hold TODCK/TOCKD TOOCECK/TOCKOCE TOSRCK/TOCKSR TOTCK/TOCKT TOTCECK/TOCKTCE Combinatorial TDOQ Sequential Delays TOCKQ TRQ TGSRQ Set/Reset TRPW Minimum Pulse Width, SR inputs 0.78 0.95 1.20 1.30 ns, Min CLK to OQ/TQ out SR pin to OQ/TQ out Global Set/Reset to Q outputs 0.54 0.80 7.60 0.61 0.90 7.60 0.71 1.05 10.51 0.80 1.19 10.51 ns ns ns D1 to OQ out or T1 to TQ out 0.78 0.87 1.01 1.15 ns D1/D2 pins Setup/Hold with respect to CLK OCE pin Setup/Hold with respect to CLK SR pin Setup/Hold with respect to CLK T1/T2 pins Setup/Hold with respect to CLK TCE pin Setup/Hold with respect to CLK 0.45/ -0.08 0.17/ -0.03 0.59/ -0.24 0.44/ -0.07 0.15/ -0.04 0.50/ -0.08 0.20/ -0.03 0.62/ -0.24 0.51/ -0.07 0.19/ -0.04 0.54/ -0.08 0.22/ -0.03 0.71/ -0.24 0.56/ -0.07 0.21/ -0.04 0.69/ -0.11 0.27/ -0.04 0.79/ -0.35 0.68/ -0.13 0.29/ -0.05 ns ns ns ns ns
Description
Speed Grade -3 -2 -1 -1L
Units
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Input Serializer/Deserializer Switching Characteristics
Table 50: ISERDES Switching Characteristics
Symbol
Setup/Hold for Control Lines TISCCK_BITSLIP/ TISCKC_BITSLIP TISCCK_CE / TISCKC_CE(2) TISCCK_CE2 / TISCKC_CE2(2) Setup/Hold for Data Lines TISDCK_D /TISCKD_D TISDCK_DDLY /TISCKD_DDLY TISDCK_D_DDR /TISCKD_D_DDR TISDCK_DDLY_DDR TISCKD_DDLY_DDR Sequential Delays TISCKO_Q Propagation Delays TISDO_DO Notes:
1. 2. Recorded at 0 tap value. TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in TRACE report.
Description
Speed Grade -3 -2 -1 -1L
Units
BITSLIP pin Setup/Hold with respect to CLKDIV CE pin Setup/Hold with respect to CLK (for CE1) CE pin Setup/Hold with respect to CLKDIV (for CE2)
0.07/ 0.15 0.20/ 0.03 0.01/ 0.27
0.08/ 0.16 0.25/ 0.04 0.01 0.29
0.09/ 0.17 0.27/ 0.04 0.01/ 0.31
0.14/ 0.17 0.31/ 0.05 -0.05/ 0.35
ns ns ns
D pin Setup/Hold with respect to CLK DDLY pin Setup/Hold with respect to CLK (using IODELAY)(1) D pin Setup/Hold with respect to CLK at DDR mode D pin Setup/Hold with respect to CLK at DDR mode (using IODELAY)(1)
0.07/ 0.08 0.10/ 0.05 0.07/ 0.08 0.10/ 0.05
0.08/ 0.09 0.12/ 0.06 0.08/ 0.09 0.12/ 0.06
0.09/ 0.11 0.14/ 0.07 0.09/ 0.11 0.14/ 0.07
0.11/ 0.19 0.16/ 0.15 0.11/ 0.19 0.16/ 0.15
ns ns ns ns
CLKDIV to out at Q pin
0.57
0.66
0.75
0.88
ns
D input to DO output pin
0.19
0.22
0.25
0.28
ns
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Output Serializer/Deserializer Switching Characteristics
Table 51: OSERDES Switching Characteristics
Symbol
Setup/Hold TOSDCK_D/TOSCKD_D TOSDCK_T/TOSCKD_T(1) TOSDCK_T2/TOSCKD_T2(1) TOSCCK_OCE/TOSCKC_OCE TOSCCK_S TOSCCK_TCE/TOSCKC_TCE Sequential Delays TOSCKO_OQ TOSCKO_TQ Combinatorial TOSDO_TTQ Notes:
1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in TRACE report.
Description
Speed Grade -3 -2 -1 -1L
Units
D input Setup/Hold with respect to CLKDIV T input Setup/Hold with respect to CLK T input Setup/Hold with respect to CLKDIV OCE input Setup/Hold with respect to CLK SR (Reset) input Setup with respect to CLKDIV TCE input Setup/Hold with respect to CLK
0.23/ -0.10 0.44/ -0.10 0.25/ -0.10 0.17/ -0.03 0.07 0.15/ -0.04
0.28/ -0.10 0.51/ -0.09 0.27/ -0.09 0.20/ -0.03 0.07 0.19/ -0.04
0.31/ -0.10 0.56/ -0.08 0.31/ -0.08 0.22/ -0.03 0.07 0.21/ -0.04
0.36/ -0.15 0.68/ -0.15 0.47/ -0.15 0.27/ -0.04 0.08 0.29/ -0.05
ns ns ns ns ns ns
Clock to out from CLK to OQ Clock to out from CLK to TQ
0.63 0.63
0.71 0.71
0.82 0.82
0.93 0.93
ns ns
T input to TQ Out
0.76
0.84
0.97
1.11
ns
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Input/Output Delay Switching Characteristics
Table 52: Input/Output Delay Switching Characteristics
Symbol
IDELAYCTRL TDLYCCO_RDY FIDELAYCTRL_REF
IDELAYCTRL_REF_PRECISION
Description
Speed Grade -3 -2 -1 -1L
Units
Reset to Ready for IDELAYCTRL Attribute REFCLK frequency = Attribute REFCLK frequency = REFCLK precision Minimum Reset pulse width 200.0(1) 300.0(1)
3.00 200 300 10 50.00
3.00 200 300 10 50.00
3.00 200 - 10 50.00
3.25 200 - 10 52.50
s MHz MHz MHz ns
TIDELAYCTRL_RPW IODELAY TIDELAYRESOLUTION
IODELAY Chain Delay Resolution Pattern dependent period jitter in delay chain for clock pattern.(2) Pattern dependent period jitter in delay chain for random data pattern (PRBS 23).(3) Pattern dependent period jitter in delay chain for random data pattern (PRBS 23).(4) 0 5
1/(32 x 2 x FREF) 0 5 0 5 0 5
ps ps per tap ps per tap ps per tap MHz ns ns ns ps ps ps
TIDELAYPAT_JIT
9
9
9
9
TIODELAY_CLK_MAX TIODCCK_CE / TIODCKC_CE TIODCK_INC/ TIODCKC_INC TIODCCK_RST/ TIODCKC_RST TIODDO_T TIODDO_IDATAIN TIODDO_ODATAIN Notes:
1. 2. 3. 4. 5.
Maximum frequency of CLK input to IODELAY CE pin Setup/Hold with respect to CK INC pin Setup/Hold with respect to CK RST pin Setup/Hold with respect to CK TSCONTROL delay to MUXE/MUXF switching and through IODELAY Propagation delay through IODELAY Propagation delay through IODELAY
500.00 0.45/ -0.09 0.23/ -0.02 0.57/ -0.08 Note 5 Note 5 Note 5
420.00 0.53/ -0.09 0.27/ -0.01 0.62/ -0.08 Note 5 Note 5 Note 5
300.00 0.65/ -0.09 0.31/ 0.00 0.69/ -0.08 Note 5 Note 5 Note 5
300.00 0.84/ -0.14 0.27/ -0.04 0.74/ -0.13 Note 5 Note 5 Note 5
Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps. When HIGH_PERFORMANCE mode is set to TRUE or FALSE. When HIGH_PERFORMANCE mode is set to TRUE When HIGH_PERFORMANCE mode is set to FALSE. Delay depends on IODELAY tap setting. See TRACE report for actual values.
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
CLB Switching Characteristics
Table 53: CLB Switching Characteristics
Symbol
Combinatorial Delays TILO An - Dn LUT address to A An - Dn LUT address to AMUX/CMUX An - Dn LUT address to BMUX_A TITO TAXA TAXB TAXC TAXD TBXB TBXD TCXB TCXD TDXD TOPCYA TOPCYB TOPCYC TOPCYD TAXCY TBXCY TCXCY TDXCY TBYP TCINA TCINB TCINC TCIND Sequential Delays TCKO TSHCKO TDICK/TCKDI TCECK_CLB/ TCKCE_CLB TSRCK/TCKSR TCINCK/TCKCIN Clock to AQ - DQ outputs Clock to AMUX - DMUX outputs 0.29 0.36 0.33 0.40 0.39 0.47 0.44 0.53 ns, Max ns, Max An - Dn inputs to A - D Q outputs AX inputs to AMUX output AX inputs to BMUX output AX inputs to CMUX output AX inputs to DMUX output BX inputs to BMUX output BX inputs to DMUX output CX inputs to CMUX output CX inputs to DMUX output DX inputs to DMUX output An input to COUT output Bn input to COUT output Cn input to COUT output Dn input to COUT output AX input to COUT output BX input to COUT output CX input to COUT output DX input to COUT output CIN input to COUT output CIN input to AMUX output CIN input to BMUX output CIN input to CMUX output CIN input to DMUX output 0.06 0.18 0.28 0.59 0.31 0.35 0.39 0.42 0.30 0.38 0.26 0.30 0.30 0.32 0.32 0.27 0.25 0.25 0.22 0.15 0.14 0.06 0.21 0.23 0.23 0.25 0.07 0.20 0.31 0.67 0.35 0.39 0.44 0.47 0.34 0.43 0.29 0.34 0.33 0.36 0.36 0.30 0.28 0.28 0.24 0.17 0.16 0.07 0.24 0.25 0.26 0.29 0.07 0.22 0.36 0.79 0.42 0.47 0.52 0.55 0.39 0.50 0.34 0.40 0.38 0.41 0.41 0.34 0.32 0.33 0.28 0.20 0.19 0.08 0.28 0.29 0.30 0.33 0.09 0.25 0.40 0.85 0.44 0.50 0.56 0.60 0.44 0.55 0.37 0.44 0.43 0.47 0.47 0.40 0.37 0.36 0.31 0.22 0.21 0.09 0.30 0.31 0.33 0.36 ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max
Description
Speed Grade -3 -2 -1 -1L
Units
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK A - D input to CLK on A - D Flip Flops CE input to CLK on A - D Flip Flops SR input to CLK on A - D Flip Flops CIN input to CLK on A - D Flip Flops 0.30/ 0.17 0.20/ 0.00 0.39/ -0.07 0.16/ 0.12 0.36/ 0.18 0.25/ 0.00 0.44/ -0.07 0.19/ 0.14 0.43/ 0.20 0.32/ 0.00 0.52/ -0.07 0.24/ 0.16 0.44/ 0.25 0.32/ 0.01 0.58/ -0.08 0.23/ 0.22 ns, Min ns, Min ns, Min ns, Min
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics Table 53: CLB Switching Characteristics (Cont'd)
Symbol
Set/Reset TSRMIN TRQ TCEO FTOG Notes:
1. 2.
A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. These items are of interest for Carry Chain applications.
Description
Speed Grade -3 -2 -1 -1L
Units
SR input minimum pulse width Delay from SR input to AQ - DQ flip-flops Delay from CE input to AQ - DQ flip-flops Toggle frequency (for export control)
0.90 0.52 0.41 1412.00
0.90 0.58 0.48 1286.40
0.97 0.68 0.59 1098.00
0.80 0.77 0.61 1098.00
ns, Min ns, Max ns, Max MHz
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 54: CLB Distributed RAM Switching Characteristics
Symbol
Sequential Delays TSHCKO TSHCKO_1 TDS/TDH TAS/TAH TWS/TWH TCECK/TCKCE Clock CLK TMPW TMCP Notes:
1. 2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. TSHCKO also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path.
Description
Speed Grade -3 -2 -1 -1L
Units
Clock to A - B outputs Clock to AMUX - BMUX outputs
0.92 1.19
1.10 1.40
1.36 1.71
1.49 1.87
ns, Max ns, Max
Setup and Hold Times Before/After Clock CLK A - D inputs to CLK Address An inputs to clock WE input to clock CE input to CLK 0.62/ 0.18 0.19/ 0.52 0.27/ 0.00 0.28/ -0.01 0.72/ 0.20 0.22/ 0.59 0.32/ 0.00 0.34/ -0.01 0.88/ 0.22 0.27/ 0.66 0.40/ 0.00 0.41/ -0.01 0.98/ 0.23 0.30/ 0.75 0.47/ -0.03 0.48/ -0.05 ns, Min ns, Min ns, Min ns, Min
Minimum pulse width Minimum clock period
0.70 1.40
0.82 1.64
1.00 2.00
1.04 2.08
ns, Min ns, Min
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 55: CLB Shift Register Switching Characteristics
Symbol
Sequential Delays TREG TREG_MUX TREG_M31 TWS/TWH TCECK/TCKCE TDS/TDH Clock CLK TMPW Notes:
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
Description
Speed Grade -3 -2 -1 -1L
Units
Clock to A - D outputs Clock to AMUX - DMUX output Clock to DMUX output via M31 output
1.11 1.37 1.08
1.30 1.60 1.27
1.58 1.93 1.55
1.74 2.12 1.74
ns, Max ns, Max ns, Max
Setup and Hold Times Before/After Clock CLK WE input CE input to CLK A - D inputs to CLK 0.05/ 0.00 0.06/ -0.01 0.64/ 0.18 0.07/ 0.00 0.08/ -0.01 0.76/ 0.21 0.09/ 0.00 0.10/ -0.01 0.94/ 0.24 0.11/ 0.03 0.12/ 0.02 1.07/ 0.23 ns, Min ns, Min ns, Min
Minimum pulse width
0.60
0.70
0.85
0.89
ns, Min
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 56: Block RAM and FIFO Switching Characteristics
Symbol
Block RAM and FIFO Clock-to-Out Delays TRCKO_DO and TRCKO_DO_REG(1) Clock CLK to DOUT output (without output register)(2)(3) Clock CLK to DOUT output (with output register)(4)(5) TRCKO_DO_ECC and TRCKO_DO_ECC_REG Clock CLK to DOUT output with ECC (without output register)(2)(3) Clock CLK to DOUT output with ECC (with output register)(4)(5) TRCKO_CASC and TRCKO_CASC_REG Clock CLK to DOUT output with Cascade (without output register)(2) Clock CLK to DOUT output with Cascade (with output register)(4) TRCKO_FLAGS TRCKO_POINTERS TRCKO_SDBIT_ECC and TRCKO_SDBIT_ECC_REG Clock CLK to FIFO flags outputs(6) Clock CLK to FIFO pointers outputs(7) 1.60 0.60 2.62 0.71 2.49 1.29 0.74 0.90 0.62 2.21 0.86 0.73 0.76 1.79 0.66 2.89 0.77 2.77 1.41 0.81 0.98 0.68 2.46 0.94 0.79 0.82 2.08 0.75 3.30 0.86 3.18 1.58 0.91 1.09 0.76 2.84 1.06 0.90 0.92 2.36 0.83 3.73 0.94 3.61 1.79 0.98 1.21 0.82 3.23 1.18 1.00 1.02 ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max
Description
Speed Grade -3 -2 -1 -1L
Units
Clock CLK to BITERR (with output register) Clock CLK to BITERR (without output register)
TRCKO_PARITY_ECC TRCKO_RDADDR_ECC and TRCKO_RDADDR_ECC_REG
Clock CLK to ECCPARITY in ECC encode only mode Clock CLK to RDADDR output with ECC (without output register) Clock CLK to RDADDR output with ECC (with output register)
Setup and Hold Times Before/After Clock CLK TRCCK_ADDR/TRCKC_ADDR TRDCK_DI/TRCKD_DI TRDCK_DI_ECC/TRCKD_DI_ECC ADDR inputs(8) DIN inputs(9) DIN inputs with block RAM ECC in standard mode(9) DIN inputs with block RAM ECC encode only(9) DIN inputs with FIFO ECC in standard mode(9) TRCCK_CLK/TRCKC_CLK TRCCK_RDEN/TRCKC_RDEN TRCCK_REGCE/TRCKC_REGCE TRCCK_RSTREG/TRCKC_RSTREG TRCCK_RSTRAM/TRCKC_RSTRAM Inject single/double bit error in ECC mode Block RAM Enable (EN) input CE input of output register Synchronous RSTREG input Synchronous RSTRAM input 0.47/ 0.27 0.84/ 0.30 0.47/ 0.30 0.68/ 0.30 0.77/ 0.30 0.90/ 0.27 0.31/ 0.26 0.18/ 0.25 0.22/ 0.23 0.32/ 0.23 0.53/ 0.29 0.95/ 0.32 0.52/ 0.32 0.75/ 0.32 0.87/ 0.32 1.02/ 0.28 0.35/ 0.27 0.19/ 0.27 0.24/ 0.24 0.36/ 0.24 0.62/ 0.32 1.11/ 0.34 0.59/ 0.34 0.85/ 0.34 1.02/ 0.34 1.20/ 0.29 0.41/ 0.30 0.22/ 0.31 0.28/ 0.26 0.41/ 0.27 0.66/ 0.34 1.26/ 0.36 0.68/ 0.36 0.97/ 0.36 1.16/ 0.36 1.56/ 0.29 0.44/ 0.31 0.24/ 0.33 0.31/ 0.27 0.46/ 0.29 ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics Table 56: Block RAM and FIFO Switching Characteristics (Cont'd)
Symbol
TRCCK_WE/TRCKC_WE TRCCK_WREN/TRCKC_WREN TRCCK_RDEN/TRCKC_RDEN Reset Delays TRCO_FLAGS TRCCK_RSTREG/TRCKC_RSTREG Maximum Frequency FMAX Block RAM (Write First and No Change modes) Block RAM (Read First mode) Block RAM (SDP mode) FMAX_CASCADE Block RAM Cascade (Write First and No Change modes) Block RAM Cascade (Read First mode) FMAX_FIFO FMAX_ECC Notes:
1. 2. 3. 4. 5. 6. 7. 8. TRACE will report all of these parameters as TRCKO_DO. TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters. These parameters also apply to synchronous FIFO with DO_REG = 0. TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1. TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR. TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible. 9. TRCKO_DI includes both A and B inputs as well as the parity inputs of A and B. 10. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT. 11. The FIFO reset must be asserted for at least three positive clock edges.
Description
Write Enable (WE) input (Block RAM only) WREN FIFO inputs RDEN FIFO inputs
Speed Grade -3
0.44/ 0.19 0.47/ 0.26 0.46/ 0.26
-2
0.47/ 0.25 0.50/ 0.27 0.50/ 0.27
-1
0.52/ 0.35 0.55/ 0.30 0.55/ 0.30
-1L
0.67/ 0.24 0.68/ 0.31 0.67/ 0.31
Units
ns, Min ns, Min ns, Min
Reset RST to FIFO Flags/Pointers(10) FIFO reset timing(11)
0.90 0.22/ 0.23
0.98 0.24/ 0.24
1.10 0.28/ 0.26
1.23 0.31/ 0.27
ns, Max ns, Min
600 525 525 550 475 600 450
540 475 475 490 425 540 400
450 400 400 400 350 450 325
340 275 275 300 235 340 250
MHz MHz MHz MHz MHz MHz MHz
FIFO in all modes Block RAM and FIFO in ECC configuration
DSP48E1 Switching Characteristics
Table 57: DSP48E1 Switching Characteristics
Symbol Description Speed -3 -2 -1 -1L Units
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_{A, ACIN; B, BCIN}_{AREG; BREG}/ TDSPCKD_{A, ACIN; B, BCIN}_{AREG; BREG} TDSPDCK_C_CREG/TDSPCKD_C_CREG TDSPDCK_D_DREG/TDSPCKD_D_DREG
{A, ACIN, B, BCIN} input to {A, B} register CLK C input to C register CLK D input to D register CLK
0.25/ 0.27 0.16/ 0.20 0.07/ 0.31
0.29/ 0.30 0.19/ 0.22 0.10/ 0.34
0.35/ 0.34 0.22/ 0.24 0.15/ 0.39
0.46/ 0.39 0.33/ 0.30 0.24/ 0.45
ns ns ns
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics Table 57: DSP48E1 Switching Characteristics (Cont'd)
Symbol Description Speed -3 -2 -1 -1L Units
Setup and Hold Times of Data Pins to the Pipeline Register Clock TDSPDCK_{A, ACIN, B, BCIN}_MREG_MULT/ TDSPCKD_{A, ACIN, B, BCIN}_MREG_MULT TDSPDCK_{A, D}_ADREG/ TDSPCKD_{A, D}_ADREG {A, ACIN, B, BCIN} input to M register CLK {A, D} input to AD register CLK 2.36/ 0.04 1.24/ 0.10 2.70/ 0.04 1.42/ 0.12 3.21/ 0.04 1.69/ 0.13 3.66/ 0.02 1.91/ 0.16 ns ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{A, ACIN, B, BCIN}_PREG_MULT/ TDSPCKD_{A, ACIN, B, BCIN}_PREG_MULT TDSPDCK_D_PREG_MULT/ TDSPCKD_D_PREG_MULT TDSPDCK_{A, ACIN, B, BCIN}_PREG/ TDSPCKD_{A, ACIN, B, BCIN}_PREG TDSPDCK_C_PREG/ TDSPCKD_C_PREG
TDSPDCK_{PCIN, CARRYCASCIN, MULTSIGNIN}_PREG/ TDSPCKD_{PCIN, CARRYCASCIN, MULTSIGNIN}_PREG Setup and Hold Times of the CE Pins
{A, ACIN, B, BCIN} input to P register CLK using multiplier D input to P register CLK {A, ACIN, B, BCIN} input to P register CLK not using multiplier C input to P register CLK {PCIN, CARRYCASCIN, MULTSIGNIN} input to P register CLK
3.83/ -0.13 3.62/ -0.47 1.59/ -0.13 1.42/ -0.10 1.23/ -0.02
4.37/ -0.13 4.13/ -0.47 1.81/ -0.13 1.61/ -0.10 1.41/ -0.02
5.20/ -0.13 4.90/ -0.47 2.15/ -0.13 1.91/ -0.10 1.67/ -0.02
5.94/ -0.24 5.61/ -0.77 2.44/ -0.24 2.16/ -0.19 1.91/ -0.07
ns ns ns ns ns
TDSPDCK_{CEA; CEB}_{AREG; BREG}/ TDSPCKD_{CEA; CEB}_{AREG; BREG} TDSPDCK_CEC_CREG/ TDSPCKD_CEC_CREG TDSPDCK_CED_DREG/ TDSPCKD_CED_DREG TDSPDCK_CEM_MREG/ TDSPCKD_CEM_MREG TDSPDCK_CEP_PREG/ TDSPCKD_CEP_PREG
Setup and Hold Times of the RST Pins
{CEA; CEB} input to {A; B} register CLK CEC input to C register CLK CED input to D register CLK CEM input to M register CLK CEP input to P register CLK
0.14/ 0.19 0.15/ 0.18 0.20/ 0.12 0.16/ 0.19 0.32/ 0.02
0.17/ 0.22 0.18/ 0.20 0.24/ 0.13 0.20/ 0.21 0.38/ 0.02
0.22/ 0.25 0.24/ 0.23 0.31/ 0.14 0.26/ 0.25 0.46/ 0.03
0.30/ 0.28 0.31/ 0.26 0.43/ 0.16 0.32/ 0.28 0.54/ 0.04
ns ns ns ns ns
TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/ TDSPCKD_{RSTA; RSTB}_{AREG; BREG} TDSPDCK_RSTC_CREG/ TDSPCKD_RSTC_CREG TDSPDCK_RSTD_DREG/ TDSPCKD_RSTD_DREG TDSPDCK_RSTM_MREG/ TDSPCKD_RSTM_MREG TDSPDCK_RSTP_PREG/ TDSPCKD_RSTP_PREG
{RSTA, RSTB} input to {A, B} register CLK RSTC input to C register CLK RSTD input to D register CLK RSTM input to M register CLK RSTP input to P register CLK
0.27/ 0.17 0.18/ 0.08 0.28/ 0.15 0.20/ 0.24 0.26/ 0.04
0.31/ 0.19 0.20/ 0.08 0.32/ 0.16 0.23/ 0.26 0.30/ 0.04
0.38/ 0.22 0.23/ 0.09 0.38/ 0.19 0.26/ 0.30 0.35/ 0.05
0.41/ 0.25 0.27/ 0.11 0.45/ 0.21 0.29/ 0.34 0.43/ 0.06
ns ns ns ns ns
Combinatorial Delays from Input Pins to Output Pins TDSPDO_{A, B}_{P, CARRYOUT}_MULT TDSPDO_D_{P, CARRYOUT}_MULT TDSPDO_{A, B}_{P, CARRYOUT} TDSPDO_{C, CARRYIN}_{P, CARRYOUT} {A, B} input to {P, CARRYOUT} output using multiplier D input to {P, CARRYOUT} output using multiplier {A, B} input to {P, CARRYOUT} output not using multiplier {C, CARRYIN} input to {P, CARRYOUT} output 3.76 3.57 1.55 1.38 4.29 4.07 1.76 1.56 5.08 4.82 2.07 1.83 5.87 5.57 2.41 2.13 ns ns ns ns
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics Table 57: DSP48E1 Switching Characteristics (Cont'd)
Symbol Description Speed -3 -2 -1 -1L Units
Combinatorial Delays from Input Pins to Cascading Output Pins TDSPDO_{A; B}_{ACOUT; BCOUT} TDSPDO_{A, B}_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_MULT
{A, B} input to {ACOUT, BCOUT} output {A, B} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier D input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier {A, B} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier {C, CARRYIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output
0.49 3.87
0.56 4.42
0.65 5.24
0.73 6.09
ns ns
TDSPDO_D_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_MULT
3.66 1.64
4.17 1.86
4.94 2.19
5.76 2.60
ns ns
TDSPDO_{A, B}_{PCOUT, CARRYCASCOUT, MULTSIGNOUT} TDSPDO__{C, CARRYIN}_{PCOUT, CARRYCASCOUT,MULTSIGNOUT}
1.46
1.66
1.95
2.32
ns
Combinatorial Delays from Cascading Input Pins to All Output Pins TDSPDO_{ACIN, BCIN}_{P, CARRYOUT}_MULT TDSPDO_{ACIN, BCIN}_{P, CARRYOUT TDSPDO_{ACIN; BCIN}_{ACOUT; BCOUT} TDSPDO_{ACIN, BCIN}_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_MULT
{ACIN, BCIN} input to {P, CARRYOUT} output using multiplier {ACIN, BCIN} input to {P, CARRYOUT} output not using multiplier {ACIN, BCIN} input to {ACOUT, BCOUT} output {ACIN, BCIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier {ACIN, BCIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier {PCIN, CARRYCASCIN, MULTSIGNIN} input to {P, CARRYOUT} output {PCIN, CARRYCASCIN, MULTSIGNIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output
3.67 1.43 0.36 3.76
4.19 1.63 0.42 4.29
4.97 1.92 0.49 5.10
5.75 2.25 0.56 5.94
ns ns ns ns
TDSPDO_{ACIN, BCIN}_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}
1.52
1.73
2.05
2.44
ns
TDSPDO_{PCIN, CARRYCASCIN, MULTSIGNIN}_
{P, CARRYOUT}
1.19 1.28
1.35 1.46
1.60 1.72
1.87 2.06
ns ns
TDSPDO_{PCIN, CARRYCASCIN, MULTSIGNIN}_ {PCOUT, CARRYCASCOUT, MULTSIGNOUT}
Clock to Outs from Output Register Clock to Output Pins TDSPCKO_{P, CARRYOUT}_PREG TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_PREG TDSPCKO_{P, CARRYOUT}_MREG TDSPCKO_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_MREG
CLK (PREG) to {P, CARRYOUT} output CLK (PREG) to {CARRYCASCOUT, PCOUT, MULTSIGNOUT} output
0.38 0.50
0.43 0.56
0.50 0.66
0.57 0.76
ns ns
Clock to Outs from Pipeline Register Clock to Output Pins CLK (MREG) to {P, CARRYOUT} output CLK (MREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output CLK (ADREG) to {P, CARRYOUT} output CLK (ADREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 1.72 1.81 1.96 2.06 2.30 2.43 2.69 2.88 ns ns
TDSPCKO_{P, CARRYOUT}_ADREG_MULT TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_ADREG_MULT
2.79 2.87
3.16 3.26
3.72 3.84
4.32 4.51
ns ns
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics Table 57: DSP48E1 Switching Characteristics (Cont'd)
Symbol
Clock to Outs from Input Register Clock to Output Pins TDSPCKO_{P, CARRYOUT}_{AREG, BREG}_MULT TDSPCKO_{P, CARRYOUT}_{AREG, BREG} TDSPCKO_{P, CARRYOUT}_CREG TDSPCKO_{P, CARRYOUT}_DREG_MULT TDSPCKO_{ACOUT; BCOUT}_{AREG; BREG} TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_{AREG, BREG}_MULT TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_{AREG, BREG} TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_DREG_MULT TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_CREG Maximum Frequency FMAX FMAX_PATDET FMAX_MULT_NOMREG FMAX_MULT_NOMREG_PATDET FMAX_PREADD_MULT_NOADREG FMAX_PREADD_MULT_NOADREG_PATDET FMAX_NOPIPELINEREG FMAX_NOPIPELINEREG_PATDET With all registers used With pattern detector Two register multiply without MREG Two register multiply without MREG with pattern detect Without ADREG Without ADREG with pattern detect Without pipeline registers (MREG, ADREG) Without pipeline registers (MREG, ADREG) with pattern detect 600 551 356 327 398 398 266 250 540 483 311 286 347 347 233 219 450 408 262 241 292 292 196 184 410 356 224 211 254 254 171 160 MHz MHz MHz MHz MHz MHz MHz MHz CLK (AREG, BREG) to {P, CARRYOUT} output using multiplier CLK (AREG, BREG) to {P, CARRYOUT} output not using multiplier CLK (CREG) to {P, CARRYOUT} output CLK (DREG) to {P, CARRYOUT} output 3.97 1.70 1.70 3.89 4.52 1.93 1.93 4.44 5.36 2.27 2.27 5.25 6.20 2.65 2.80 6.07 ns ns ns ns
Description
Speed -3 -2 -1 -1L
Units
Clock to Outs from Input Register Clock to Cascading Output Pins CLK (AREG, BREG) to {P, CARRYOUT} output CLK (AREG, BREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier CLK (AREG, BREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier CLK (DREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier CLK (CREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 0.66 4.05 0.76 4.63 0.89 5.49 1.01 6.39 ns ns
1.79
2.03
2.40
2.84
ns
3.98
4.54
5.38
6.26
ns
1.78
2.03
2.40
2.99
ns
Configuration Switching Characteristics
Table 58: Configuration Switching Characteristics
Symbol Power-up Timing Characteristics
TPL(1) TPOR(1) TICCK TPROGRAM Program Latency Power-on-Reset CCLK (output) delay Program Pulse Width 5 15/55 400 250 5 15/55 400 250 5 15/55 400 250 5 15/55 400 250 ms, Max ms, Min/Max ns, Min ns, Min
Description
Speed Grade -3 -2 -1 -1L
Units
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics Table 58: Configuration Switching Characteristics (Cont'd)
Symbol Description Speed Grade -3 -2 -1 -1L Units
Master/Slave Serial Mode Programming Switching
TDCCK/TCCKD TDSCCK/TSCCKD TCCO FMCCK FMCCKTOL FMSCCK TSMDCCK/TSMCCKD TSMCSCCK/TSMCCKCS TSMCCKW/TSMWCCK TSMCKCSO TSMCO TSMCKBY FSMCCK FRBCCK FMCCKTOL DIN Setup/Hold, slave mode DIN Setup/Hold, master mode DOUT at 2.5V DOUT at 1.8V Maximum CCLK frequency, serial modes Frequency Tolerance, master mode with respect to nominal CCLK. Slave mode external CCLK 4.0/0.0 4.0/0.0 6 6 100 55 100 4.0/0.0 4.0/0.0 6 6 100 55 100 4.0/0.0 4.0/0.0 6 6 100 55 100 4.5/0.0 5.0/0.0 7 7 100 55 100 ns, Min ns, Min ns, Max ns, Max MHz, Max % MHz
SelectMAP Mode Programming Switching
SelectMAP Data Setup/Hold CSI_B Setup/Hold RDWR_B Setup/Hold CSO_B clock to out (330 pull-up resistor required) CCLK to DATA out in readback at 2.5V CCLK to DATA out in readback at 1.8V CCLK to BUSY out in readback at 2.5V CCLK to BUSY out in readback at 1.8V Maximum Frequency with respect to nominal CCLK Maximum Readback Frequency with respect to nominal CCLK Frequency tolerance, master mode with respect to nominal CCLK 4.0/0.0 4.0/0.0 4.0/0.0 4.0/0.0 4.0/0.0 4.0/0.0 10.0/0.0 6 6 6 6 6 100 100 55 5.5/0.0 4.5/0.0 13.5/0.0 7 7 7 7 7 70 100 55 ns, Min ns, Min ns, Min ns, Min ns, Max ns, Max ns, Max ns, Max MHz, Max MHz, Max %
10.0/0.0 10.0/0.0 6 6 6 6 6 100 100 55 6 6 6 6 6 100 100 55
Boundary-Scan Port Timing Specifications
TTAPTCK/TTCKTAP TTCKTDO TMS and TDI Setup time before TCK/ Hold time after TCK TCK falling edge to TDO output valid at 2.5V TCK falling edge to TDO output valid at 1.8V FTCK FTCKB_MIN Maximum configuration TCK clock frequency Minimum boundary-scan TCK clock frequency when using IEEE Std 1149.6 (AC-JTAG). Minimum operating temperature for IEEE Std 1149.6 is 0C. Maximum boundary-scan TCK clock frequency 3.0/2.0 6 6 66 15 3.0/2.0 6 6 66 15 3.0/2.0 6 6 66 15 4.0/2.0 7 7 66 15 ns, Min ns, Max ns, Max MHz, Max MHz, Min
FTCKB
66
66
66
66
MHz, Max
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics Table 58: Configuration Switching Characteristics (Cont'd)
Symbol Description Speed Grade -3 -2 -1 -1L Units
BPI Master Flash Mode Programming Switching
TBPICCO(2) ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B outputs valid after CCLK rising edge at 2.5V ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B outputs valid after CCLK rising edge at 1.8V TBPIDCC/TBPICCD TINITADDR Setup/Hold on D[15:0] data input pins Minimum period of initial ADDR[25:0] address cycles 6 6 6 7 ns
6
6
6
7
ns
4.0/0.0 3
4.0/0.0 3
4.0/0.0 3
5.0/0.0 3
ns CCLK cycles
SPI Master Flash Mode Programming Switching
TSPIDCC/TSPIDCCD TSPICCM TSPICCFC TFSINIT/TFSINITH DIN Setup/Hold before/after the rising CCLK edge MOSI clock to out at 2.5V MOSI clock to out at 1.8V FCS_B clock to out at 2.5V FCS_B clock to out at 1.8V FS[2:0] to INIT_B rising edge Setup and Hold 3.0/0.0 6 6 6 6 2 3.0/0.0 6 6 6 6 2 3.0/0.0 6 6 6 6 2 3.5/0.0 7 7 7 7 2 ns ns ns ns ns s
CCLK Output (Master Modes)
TMCCKL TMCCKH Master CCLK clock Low time duty cycle Master CCLK clock High time duty cycle 45/55 45/55 45/55 45/55 45/55 45/55 45/55 45/55 %, Min/Max %, Min/Max
CCLK Input (Slave Modes)
TSCCKL TSCCKH FDCK TMMCMDCK_DADDR/ TMMCMCKD_DADDR TMMCMDCK_DI/TMMCMCKD_DI TMMCMDCK_DEN/TMMCMCKD_DEN TMMCMDCK_DWE/TMMCMCKD_DWE TMMCMCKO_DO TMMCMCKO_DRDY Notes:
1. 2. 3. To support longer delays in configuration, use the design solutions described in Virtex-6 FPGA Configuration User Guide. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O. DO will hold until next DRP operation.
Slave CCLK clock minimum Low time Slave CCLK clock minimum High time
2.5 2.5
2.5 2.5
2.5 2.5
2.5 2.5
ns, Min ns, Min
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
Maximum frequency for DCLK DADDR Setup/Hold DI Setup/Hold DEN Setup/Hold time DWE Setup/Hold time CLK to out of DO(3) CLK to out of DRDY 200 1.25/ 0.00 1.25/ 0.00 1.25/ 0.00 1.25/ 0.00 2.60 0.32 200 1.40/ 0.00 1.40/ 0.00 1.40/ 0.00 1.40/ 0.00 3.02 0.34 200 1.63/ 0.00 1.63/ 0.00 1.63/ 0.00 1.63/ 0.00 3.64 0.38 200 1.64/ 0.00 1.64/ 0.00 1.64/ 0.00 1.64/ 0.00 3.68 0.38 MHz ns ns ns ns ns ns
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Clock Buffers and Networks
Table 59: Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol
TBCCCK_CE/TBCCKC_CE(1) TBCCCK_S/TBCCKC_S(1) TBCCKO_O(2) Maximum Frequency FMAX Notes:
1. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks. TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values.
Description
CE pins Setup/Hold S pins Setup/Hold BUFGCTRL delay from I0/I1 to O
Speed Grade -3
0.11/ 0.00 0.11/ 0.00 0.07
-2
0.13/ 0.00 0.13/ 0.00 0.08
-1
0.16/ 0.00 0.16/ 0.00 0.10
-1L
0.13/ 0.00 0.13/ 0.00 0.10
Units
ns ns ns
Global clock tree (BUFG)
800
750
700
667
MHz
2.
Table 60: Input/Output Clock Switching Characteristics (BUFIO)
Symbol
TBIOCKO_O Maximum Frequency FMAX I/O clock tree (BUFIO) 800 800 710 710 MHz
Description
Clock to out delay from I to O
Speed Grade -3
0.14
-2
0.16
-1
0.18
-1L
0.21
Units
ns
Table 61: Regional Clock Switching Characteristics (BUFR)
Symbol
TBRCKO_O TBRCKO_O_BYP TBRDO_O Maximum Frequency FMAX(1) Notes:
1. The maximum input frequency to the BUFR is the BUFIO FMAX frequency.
Description
Clock to out delay from I to O Clock to out delay from I to O with Divide Bypass attribute set Propagation delay from CLR to O
Speed Grade -3
0.56 0.28 0.69
-2
0.62 0.31 0.74
-1
0.73 0.36 0.80
-1L
0.82 0.41 1.12
Units
ns ns ns
Regional clock tree (BUFR)
500
420
300
300
MHz
Table 62: Horizontal Clock Buffer Switching Characteristics (BUFH)
Symbol
TBHCKO_O TBHCCK_CE/TBHCKC_CE Maximum Frequency FMAX Horizontal clock buffer (BUFH) 800 750 700 667 MHz
Description
BUFH delay from I to O CE pin Setup and Hold
Speed Grade -3
0.10 0.04/ 0.04
-2
0.11 0.04/ 0.04
-1
0.13 0.05/ 0.05
-1L
0.15 0.04/ 0.04
Units
ns ns
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
MMCM Switching Characteristics
Table 63: MMCM Specification
Symbol
FINMAX FINMIN FINJITTER FINDUTY
Description
Maximum Input Clock Frequency Minimum Input Clock Frequency Maximum Input Clock Period Jitter Allowable Input Duty Cycle: 19--49 MHz Allowable Input Duty Cycle: 50--199 MHz Allowable Input Duty Cycle: 200--399 MHz Allowable Input Duty Cycle: 400--499 MHz Allowable Input Duty Cycle: >500 MHz
Speed Grade -3
800 10
-2
750 10
-1
700 10
-1L
700 10
Units
MHz MHz
< 20% of clock input period or 1 ns Max 25/75 30/70 35/65 40/60 45/55 0.01 550 600 1600 1.00 4.00 0.12 0.01 500 600 1440 1.00 4.00 0.12 0.01 450 600 1200 1.00 4.00 0.12 Note 1 0.01 450 600 1200 1.00 4.00 0.12 % % % % % MHz MHz MHz MHz MHz MHz ns
FMIN_PSCLK FMAX_PSCLK FVCOMIN FVCOMAX FBANDWIDTH TSTATPHAOFFSET TOUTJITTER TOUTDUTY TLOCKMAX FOUTMAX FOUTMIN TEXTFDVAR RSTMINPULSE FPFDMAX
Minimum Dynamic Phase Shift Clock Frequency Maximum Dynamic Phase Shift Clock Frequency Minimum MMCM VCO Frequency Maximum MMCM VCO Frequency Low MMCM Bandwidth at High MMCM Bandwidth at Jitter(3) Precision(4) Typical(1) Typical(1) Outputs(2)
Static Phase Offset of the MMCM MMCM Output
MMCM Output Clock Duty Cycle MMCM Maximum Lock Time
0.15 100 800 4.69
0.20 100 750 4.69
0.20 100 700 4.69
0.20 100 700 4.69
ns s MHz MHz
MMCM Maximum Output Frequency MMCM Minimum Output Frequency(5)(6)
External Clock Feedback Variation Minimum Reset Pulse Width Maximum Frequency at the Phase Frequency Detector with Bandwidth Set to High or Optimized Maximum Frequency at the Phase Frequency Detector with Bandwidth Set to Low 1.5
< 20% of clock input period or 1 ns Max 1.5 500 300 10.00 1.5 450 300 10.00 1.5 450 300 10.00 ns MHz MHz MHz
550 300 10.00
FPFDMIN TFBDELAY TMMCMDCK_PSEN/ TMMCMCKD_PSEN TMMCMDCK_PSINCDEC/ TMMCMCKD_PSINCDEC TMMCMCKO_PSDONE Notes:
1. 2. 3. 4. 5. 6.
Minimum Frequency at the Phase Frequency Detector Maximum Delay in the Feedback Path Setup and Hold of Phase Shift Enable Setup and Hold of Phase Shift Increment/Decrement Phase Shift Clock-to-Out of PSDONE
3 ns Max or one CLKIN cycle 1.04 0.00 1.04 0.00 0.32 1.04 0.00 1.04 0.00 0.34 1.04 0.00 1.04 0.00 0.38 1.04 0.00 1.04 0.00 0.38 ns ns ns
The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. The static offset is measured between any MMCM outputs with identical phase. Values for this parameter are available in the Architecture Wizard. Includes global clock buffer. Calculated as FVCO/128 assuming output duty cycle is 50%. When CASCADE4_OUT = TRUE, FOUTMIN is 0.036 MHz.
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Virtex-6 Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 64. Values are expressed in nanoseconds unless otherwise noted. Table 64: Global Clock Input to Output Delay Without MMCM
Symbol Description Device Speed Grade -3 -2 -1 -1L Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without MMCM. TICKOF Global Clock input and OUTFF without MMCM XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
4.91 4.89 5.02 5.02 5.30 N/A N/A 5.40 N/A 5.18 5.20 5.38 N/A
5.32 5.33 5.46 5.46 5.75 6.02 6.26 5.85 6.01 5.63 5.66 5.84 5.85
5.88 6.00 6.13 6.13 6.43 6.72 6.97 6.54 6.71 6.30 6.34 6.53 6.56
6.02 6.13 6.27 6.27 6.37 6.60 6.87 6.49 6.61 N/A N/A N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 65: Global Clock Input to Output Delay With MMCM
Symbol Description Device Speed Grade -3 -2 -1 -1L Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with MMCM. TICKOFMMCMGC Global Clock Input and OUTFF with MMCM XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T Notes:
1. 2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. MMCM output jitter is already included in the timing calculation.
2.34 2.35 2.36 2.36 2.37 N/A N/A 2.35 N/A 2.36 2.46 2.39 N/A
2.50 2.51 2.52 2.52 2.53 2.55 2.54 2.51 2.43 2.53 2.63 2.59 2.54
2.77 2.78 2.79 2.79 2.79 2.82 2.82 2.79 2.70 2.80 2.91 2.83 2.81
2.85 2.87 2.88 2.88 2.89 2.93 2.92 2.87 2.79 N/A N/A N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 66: Clock-Capable Clock Input to Output Delay With MMCM
Symbol Description Device Speed Grade -3 -2 -1 -1L Units
LVCMOS25 Clock-capable Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with MMCM. TICKOFMMCMCC Clock-capable Clock Input and OUTFF with MMCM XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T Notes:
1. 2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. MMCM output jitter is already included in the timing calculation.
2.22 2.24 2.24 2.24 2.25 N/A N/A 2.23 N/A 2.25 2.35 2.27 N/A
2.38 2.39 2.40 2.40 2.42 2.43 2.42 2.38 2.30 2.41 2.51 2.43 2.41
2.63 2.65 2.65 2.65 2.65 2.68 2.69 2.65 2.57 2.67 2.78 2.69 2.68
2.72 2.74 2.75 2.75 2.76 2.80 2.79 2.73 2.66 N/A N/A N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Virtex-6 Device Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 67. Values are expressed in nanoseconds unless otherwise noted. Table 67: Global Clock Input Setup and Hold Without MMCM
Symbol Description Device Speed Grade -3 -2 -1 -1L Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSFD/ TPHFD Full Delay (Legacy Delay or Default Delay) Global Clock Input and IFF(2) without MMCM XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. IFF = Input Flip-Flop or Latch A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
1.33/ 0.03 1.31/ -0.08 1.36/ -0.11 1.36/ -0.11 1.79/ -0.28 N/A N/A 1.75/ -0.09 N/A 1.93/ -0.22 1.81/ -0.33 1.93/ -0.11 N/A
1.44/ 0.03 1.54/ -0.08 1.60/ -0.11 1.60/ -0.11 1.87/ -0.28 2.22/ -0.12 2.19/ -0.24 1.85/ -0.09 2.14/ -0.14 2.04/ -0.22 2.11/ -0.33 2.04/ -0.11 2.38/ -0.12
1.75/ 0.03 1.88/ -0.08 1.97/ -0.11 1.97/ -0.11 2.17/ -0.28 2.36/ -0.12 2.35/ -0.24 2.06/ -0.09 2.31/ -0.14 2.25/ -0.22 2.56/ -0.33 2.25/ -0.11 2.54/ -0.12
2.18/ -0.22 2.31/ -0.12 2.40/ -0.25 2.40/ -0.25 2.48/ -0.24 2.77/ -0.26 2.71/ -0.21 2.47/ -0.24 2.71/ -0.30 N/A N/A N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns
2. 3.
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 68: Global Clock Input Setup and Hold With MMCM
Symbol Description Device Speed Grade -3 -2 -1 -1L Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSMMCMGC/ TPHMMCMGC No Delay Global Clock Input and IFF(2) with MMCM XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. IFF = Input Flip-Flop or Latch Use IBIS to determine any duty-cycle distortion incurred using various standards.
1.45/ -0.18 1.53/ -0.18 1.54/ -0.17 1.54/ -0.17 1.55/ -0.18 N/A N/A 1.56/ -0.18 N/A 1.52/ -0.17 1.52/ -0.12 1.68/ -0.16 N/A
1.57/ -0.18 1.65/ -0.18 1.66/ -0.17 1.66/ -0.17 1.67/ -0.18 1.84/ -0.17 2.26/ -0.13 1.68/ -0.18 1.85/ -0.23 1.64/ -0.17 1.64/ -0.12 1.81/ -0.16 1.81/ -0.16
1.72/ -0.18 1.81/ -0.18 1.82/ -0.17 1.82/ -0.17 1.83/ -0.18 2.02/ -0.17 2.49/ -0.13 1.84/ -0.18 2.03/ -0.23 1.80/ -0.17 1.80/ -0.12 1.99/ -0.16 1.99/ -0.16
1.78/ -0.08 1.87/ -0.07 1.87/ -0.08 1.87/ -0.08 1.87/ -0.07 2.06/ -0.06 2.06/ -0.03 1.89/ -0.08 2.07/ -0.13 N/A N/A N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns
2. 3.
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 69: Clock-Capable Clock Input Setup and Hold With MMCM
Symbol Description Device Speed Grade -3 -2 -1 -1L Units
Input Setup and Hold Time Relative to Clock-capable Clock Input Signal for LVCMOS25 Standard.(1) TPSMMCMCC/ TPHMMCMCC No Delay Clock-capable Clock Input and XC6VLX75T IFF(2) with MMCM XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. IFF = Input Flip-Flop or Latch Use IBIS to determine any duty-cycle distortion incurred using various standards.
1.56/ -0.25 1.64/ -0.25 1.65/ -0.24 1.65/ -0.24 1.66/ -0.25 N/A N/A 1.67/ -0.25 N/A 1.63/ -0.24 1.63/ -0.19 1.80/ -0.23 N/A
1.69/ -0.25 1.78/ -0.25 1.79/ -0.24 1.79/ -0.24 1.79/ -0.25 1.97/ -0.24 2.39/ -0.20 1.80/ -0.25 1.98/ -0.29 1.76/ -0.24 1.76/ -0.19 1.94/ -0.23 1.94/ -0.23
1.86/ -0.25 1.95/ -0.25 1.96/ -0.24 1.96/ -0.24 1.97/ -0.25 2.16/ -0.24 2.63/ -0.20 1.98/ -0.25 2.17/ -0.29 1.94/ -0.24 1.94/ -0.19 2.13/ -0.23 2.13/ -0.23
1.91/ -0.15 2.00/ -0.14 2.01/ -0.15 2.01/ -0.15 2.02/ -0.15 2.19/ -0.14 2.21/ -0.10 2.03/ -0.16 2.21/ -0.20 N/A N/A N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns
2. 3.
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Clock Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-6 FPGA clock transmitter and receiver data-valid windows. Table 70: Duty Cycle Distortion and Clock-Tree Skew
Symbol
TDCD_CLK TCKSKEW
Description
Global Clock Tree Duty Cycle Distortion(1) Global Clock Tree Skew(2)
Device
All XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T
Speed Grade -3
0.12 0.15 0.25 0.26 0.26 0.28 N/A N/A 0.27 N/A 0.25 0.35 0.45 N/A 0.08 0.03 0.10 0.15
-2
0.12 0.16 0.26 0.27 0.27 0.29 0.50 0.51 0.28 0.39 0.26 0.37 0.47 0.46 0.08 0.03 0.12 0.15
-1
0.12 0.18 0.29 0.31 0.31 0.31 0.54 0.56 0.32 0.44 0.29 0.41 0.52 0.51 0.08 0.03 0.23 0.15
-1L
0.12 0.17 0.28 0.30 0.30 0.31 0.54 0.56 0.30 0.42 N/A N/A N/A N/A 0.08 0.02 0.12 0.15
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TDCD_BUFIO TBUFIOSKEW TBUFIOSKEW2 TDCD_BUFR Notes:
1.
I/O clock tree duty cycle distortion I/O clock tree skew across one clock region I/O clock tree skew across three clock regions Regional clock tree duty cycle distortion
All All All All
2.
These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application.
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 71: Package Skew
Symbol
TPKGSKEW Package
Description
Skew(1)
Device
XC6VLX75T
Package
FF484 FF784 FF484 FF784 FF1156 FF784 FF1156 FF784 FF1156 FF1759 FF1156 FF1759 FF1759 FF1760 FF1760 FF1156 FF1759 FF1156 FF1759 FF1154 FF1155 FF1923 FF1154 FF1155 FF1923 FF1924 FF1923 FF1924
Value
82 108 78 126 165 128 131 146 182 187 137 156 159 202 194 139 162 131 161 159 220 172 227 220
Units
ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T
XC6VHX380T
XC6VHX565T Notes:
1. 2.
These values represent the worst-case skew between any two SelectIO resources in the package: shortest flight time to longest flight time from Pad to Ball (7.0 ps per mm). Package trace length information is available for these device/package combinations. This information can be used to deskew the package.
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 72: Sample Window
Symbol
TSAMP TSAMP_BUFIO Notes:
1. This parameter indicates the total sampling error of Virtex-6 FPGA DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers' edges of operation. These measurements include: - CLK0 MMCM jitter - MMCM accuracy (phase offset) - MMCM phase shift resolution These measurements do not include package or clock tree skew. This parameter indicates the total sampling error of Virtex-6 FPGA DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers' edges of operation. These measurements do not include package or clock tree skew.
Description
Sampling Error at Receiver Pins(1) Sampling Error at Receiver Pins using BUFIO(2)
Device
All All
Speed Grade -3
510 300
-2
560 350
-1
610 400
-1L
670 440
Units
ps ps
2.
Table 73: Pin-to-Pin Setup/Hold and Clock-to-Out
Symbol Description Speed Grade -3 -2 -1 -1L Units
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO TPSCS/TPHCS Setup/Hold of I/O clock -0.28 1.09 -0.28 1.16 -0.28 1.33 -0.18 1.79 ns
Pin-to-Pin Clock-to-Out Using BUFIO TICKOFCS Clock-to-Out of I/O clock 4.22 4.59 5.22 5.63 ns
Revision History
The following table shows the revision history for this document:
Date
06/24/09 07/16/09
Version
1.0 1.1 Initial Xilinx release.
Description of Revisions
Revised the maximum VCCAUX and VIN numbers in Table 2, page 2. Removed empty column from Table 3, page 2. Revised specifications on Table 20, page 11. Updated Table 38, page 20 and added notes 1 and 2. Revised TDLYCCO_RDY, TIDELAYCTRL_RPW, and TIDELAYPAT_JIT in Table 52, page 35. Updated Table 57, page 40 to more closely match the DSP48E1 speed specifications. Updated TTAPTCK/TTCKTAP in Table 58, page 43. Updated XC6VLX130T parameters in Table 67 through Table 69, page 52. Added values for -1L voltages and speed grade in all pertinent tables. Added VFS and notes to Table 1 and Table 2. Removed DVPPIN from the example in Figure 2. Added networking applications to Table 41, page 23. Changed and added to the block RAM FMAX section in Table 56, page 39 including removing Note 12. Changed FPFDMAX values and corrected units for TSTATPHAOFFSET and TOUTDUTY in Table 63, page 47. Updated Table 70, page 53. Added Virtex-6 HXT devices to entire document including GTH Transceiver Specifications. Updated speed specifications as described in Switching Characteristics, includes changes in Table 50, Table 56, Table 57, and Table 65 through Table 69. Comprehensive changes to Table 14, Table 15, and Table 16. Added conditions to DVPPOUT and revised description of TOSKEW in Table 17. Removed VISE specification and note from Table 18. Added note 3 to Table 23. Updated note 3 in Table 24. Updated LVCMOS25 delays in Table 44. Updated specification for TIOTPHZ in Table 45. Removed TBUFHSKEW from Table 70, page 53 and added values for TBUFIOSKEW. Added values in Table 73.
08/19/09
1.2
09/16/09
2.0
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Date
01/18/10
Version
2.1
Description of Revisions
Changed absolute maximum ratings for both VIN and VTS in Table 1. Added data to Table 3. Added data to Table 5. Updated SSTL15 in Table 7. Updated VOCM and VOD values in Table 8. Added eFUSE endurance Table 12. Added values to VMGTREFCLK and VIN in Table 13, page 9. Added values and updated tables in the GTX Transceiver Specifications and GTH Transceiver Specifications sections. Added Table 27 and Figure 4. Revised parameters and values in Table 39. Updated Table 40, page 21. Added data to Table 41. Updated speed specification to v1.04 with appropriate changes to Table 42 and Table 43 including production release of the XC6VLX240T for -1 and -2 speed grades. Speed specification changes and numerous updates also made to Table 44, and Table 48 through Table 70. Added data to Table 72 and Table 73. Revised description of CIN in Table 3. Clarified values in Table 5. Fixed SDR LVDS unit error in Table 41. Added note 3 and update value of n in Table 3. Clarified simultaneous power-down in Power-On Power Supply Requirements. Updated external reference junction temperatures in Table 40, Analog-to-Digital Specifications. Updated speed specification to v1.05 with appropriate changes to Table 42 and Table 43 including production release of the XC6VLX130T for -1 and -2 speed grades. Fixed note 4 in Table 47. Increased the -2 specification for FIDELAYCTRL_REF and clarified units for TIDELAYPAT_JIT in Table 52. Added note 1 to Table 61. Updated FRXREC in Table 22. Revised FIDELAYCTRL_REF in Table 52. Removed TRCKO_PARITY_ECC: Clock CLK to ECCPARITY in standard ECC mode row in Table 56. Added XC6VLX130T values to Table 71. Added XC6VLX195T data to Table 5. Updated values in Table 22 including adding note 2 and note 3. Updated speed specification to v1.06 with appropriate changes to Table 42 and Table 43 including production release of the XC6VLX195T for -1 and -2 speed grades. Added XC6VLX195T values to Table 71. Changed Table 42 and Table 43 to production status on the -3 speed grade XC6VLX130T, XC6VLX195T, and XC6VLX240T devices. Added XC6VHX250Tdata to Table 4 and Table 71. Added Note 6 to Table 63. Changed Table 42 and Table 43 to production status on the XC6VLX75T, XC6VLX365T, XC6VLX550T, XC6VLX760, XC6VSX315T, and XC6VSX475T devices using ISE 12.2 software with speed specification v1.08. Updated VCMOUTDC equation to MGTAVTT - DVPPOUT/4 in Table 17. Updated some -3, -2, -1 specifications in Table 64 through Table 71. Added and updated -1L specifications to Table 41 and for most switching characteristics tables. Changed Table 42 and Table 43 to production status on the -1L speed grade for the XC6VLX130T, XC6VLX195T, XC6VLX240T, XC6VLX365T, and XC6VLX550T devices using ISE 12.2 software with current speed specifications. Also updated the speed specifications for XC6VLX75T, XC6VLX550T, and XC6VSX315T. Updated VCCINT specifications for -1L speed grade industrial temperature range devices in Table 2. In Table 32, changed FGPLLMAX specification in -3 column from 5.951 to 5.591. In Table 40, changed FMAX for the DCLK from 250 MHz to 80 MHz. The specification change in version 2.9, Table 40 is described in XCN10032, Virtex-6 FPGA: GTX Transceiver User Guide, Family Data Sheet (SYSMON DCLK), and JTAG ID Changes In this version (2.10), -1L(I) data is added to Table 4 and clarified in Note 2. Changed Table 42 and Table 43 to production status on the -1L speed grade XC6VLX75T, XC6VLX760, XC6VSX315T, and XC6VSX475T devices using ISE 12.3 software with current speed specifications. Revised the XC6VLX760 -1L speed specification for TPHMMCMGC in Table 68 and TPHMMCMCC in Table 69.
02/09/10 04/12/10
2.2 2.3
05/11/10
2.4
05/26/10
2.5
07/16/10
2.6
07/23/10
2.7
07/30/10
2.8
09/20/10 10/18/10
2.9 2.10
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS.
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